AD7723
CLKIN
FSI
SCO
(CFMT = 0)
FSO
SDO
32 CLKIN CYCLES
t8
t14
t11
16 CLKIN CYCLES
t12
16 CLKIN CYCLES
t13
D3 D2 D1 D0 D15 D14 D13
D3 D2 D1 D0 D15 D14 D13
D3 D2 D1 D0 D15
Figure 6. Serial Mode 3: Timing for Frame Sync Input, Frame Sync Output, Serial Clock Output, and Serial Data Output (See Table 3 for Control Inputs, TSI = DOE)
Table 3. Serial Interface (MODE1 = 0, MODE2 = 0)
Serial Mode
1
1
2
2
3
Decimation Ratio (SLDR)
32
32
32
32
16
Digital Filter Mode (SLP)
Low Pass
Band Pass
Low Pass
Band Pass
Low Pass
SCO Frequency (SCR)
fCLKIN
fCLKIN
fCLKIN/2
fCLKIN/2
fCLKIN
Output Data Rate
fCLKIN/32
fCLKIN/32
fCLKIN/32
fCLKIN/32
fCLKIN/16
Control Inputs
SLDR SLP SCR
1
10
1
00
1
11
1
01
0
10
Table 4. Parallel Interface
Digital Filter Mode
Band Pass
Low Pass
Low Pass
Decimation Ratio
32
32
16
Output Data Rate
fCLKIN/32
fCLKIN/32
fCLKIN/16
Control Inputs
MODE1
MODE2
0
1
1
0
1
1
DOE
t15
t16
SDO
Figure 7. Serial Mode Timing for Data Output Enable and Serial Data Output
Rev. C | Page 8 of 32