SJA1000 Ver la hoja de datos (PDF) - Philips Electronics
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Lista de partido
SJA1000 Datasheet PDF : 68 Pages
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Philips Semiconductors
Stand-alone CAN controller
Product specification
SJA1000
5 PINNING
SYMBOL
PIN
DESCRIPTION
AD7 to AD0
ALE/AS
CS
RD/E
WR
CLKOUT
VSS1
XTAL1
XTAL2
MODE
VDD3
TX0
TX1
VSS3
INT
RST
VDD2
RX0, RX1
VSS2
VDD1
2, 1, 28 to 23
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19, 20
21
22
multiplexed address/data bus
ALE input signal (Intel mode), AS input signal (Motorola mode)
chip select input, LOW level allows access to the SJA1000
RD signal (Intel mode) or E enable signal (Motorola mode) from the microcontroller
WR signal (Intel mode) or RD/WR signal (Motorola mode) from the microcontroller
clock output signal produced by the SJA1000 for the microcontroller; the clock
signal is derived from the built-in oscillator via the programmable divider; the clock
off bit within the clock divider register allows this pin to disable
ground for logic circuits
input to the oscillator amplifier; external oscillator signal is input via this pin; note 1
output from the oscillator amplifier; the output must be left open-circuit when an
external oscillator signal is used; note 1
mode select input
1 = selects Intel mode
0 = selects Motorola mode
5 V supply for output driver
output from the CAN output driver 0 to the physical bus line
output from the CAN output driver 1 to the physical bus line
ground for output driver
interrupt output, used to interrupt the microcontroller; INT is active LOW if any bit of
the internal interrupt register is set; INT is an open-drain output and is designed to
be a wired-OR with other INT outputs within the system; a LOW level on this pin will
reactivate the IC from sleep mode
reset input, used to reset the CAN interface (active LOW); automatic power-on reset
can be obtained by connecting RST via a capacitor to VSS and a resistor to VDD
(e.g. C = 1 µF; R = 50 kΩ)
5 V supply for input comparator
input from the physical CAN-bus line to the input comparator of the SJA1000;
a dominant level will wake up the SJA1000 if sleeping; a dominant level is read, if
RX1 is higher than RX0 and vice versa for the recessive level; if the CBP bit (see
Table 49) is set in the clock divider register, the CAN input comparator is bypassed
to achieve lower internal delays if an external transceiver circuitry is connected to
the SJA1000; in this case only RX0 is active; HIGH is interpreted as recessive level
and LOW is interpreted as dominant level
ground for input comparator
5 V supply for logic circuits
Note
1. XTAL1 and XTAL2 pins should be connected to VSS1 via 15 pF capacitors.
2000 Jan 04
5
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