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M66238FP

STANDARD CLOCK GENERATOR WITH PLL FREQUENCY SYNTHESIZER

MITSUBISHI ELECTRIC  

MITSUBISHI 〈DIGITAL ASSP〉

M66238FP

STANDARD CLOCK GENERATOR WITH PLL FREQUENCY SYNTHESIZER

PIN DESCRIPTIONS

Pin name

Name

RESET

Reset input

CS

Chip select input

SIN

Serial data input

SCLK

Serial clock input

XIN

Clock input

XOUT

TR

CKOB

Clock output

Trigger input

Clock output

CKO/PLLO PLL output

PULSE

CPOUT

CPIN

RV

TCKI

TCKO

UP

DOWN

DVCC

DGND

VCCO

GNDO

AVCC

AGND

One-shot pulse output

Filter connect pin

Filter connect pin

VCO load output

Test pin

Test pin

Test pin

Test pin

Digital power supply pin

Digital GND pin

Sync output power supply pin

Sync output GND pin

Analog power supply pin

Analog GND pin

I/O

Input

Input

Input

Input

Input

Output

Input

Output

Output

Output

Output

Input

Output

Input

Output

Output

Output

—

—

—

—

—

—

Function

Initialize M66238 internal status.

Transfer serial data when CS=“L”.

Synchronize 32-bit serial data from MCU with SCK, and enter.

Enter a sync clock for writing 32-bit serial data.

Used by connecting crystal oscillator between XIN and XOUT. When using an

external clock signal, connect the clock oscillator to XIN pin and open XOUT pin.

Trigger input for clock sync.

Output an inverted CKO signal.

CKO outputs a clock synchronized with a trigger signal and PLLO outputs a PLL

oscillator clock as it is.

Output a one-shot pulse synchronized with a CKO signal.

Connect a low pass filter to charge pump output.

Low pass filter input pin.

Connect a load resistor for VCO circuit operation between RV and GND.

Shipping test pin. Connect to GND when use.

Shipping test pin. Keep open when use.

Shipping test pin. Keep open when use.

Shipping test pin. Keep open when use.

Digital power supply pin.

Digital GND pin.

Power supply pin for sync output.

GND pin for sync output.

Analog power supply pin.

Analog GND pin.

LIST OF REGISTER SETTING COMMANDS

A1

A0

Setting

Setting of CKO/PLLO dividing ratio,

0

0

PLL synthesizer 15-bit generation

dividing ratio and reference clock

generation 12-bit dividing ratio.

Setting of one-shot pulse polarity and

width, setting of trigger edge, HALT of

1

0

entire M66238, HALT of charge pump

and VCO, phase comparator output

UP/DOWN, CKO/PLLO switching.

1

1

Dummy trigger generation command

SERIAL DATA WRITE TIMING

CS

SCLK

SIN

A0 A1 D0 D1 D2 D3 D4 D5 D6

Address bit

Data bit

D26 D27 D28 D29

2

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