AD1853
L/RCLK
INPUT
BCLK
INPUT
SDATA
LSB
INPUT
LEFT CHANNEL
RIGHT CHANNEL
MSB MSB–1 MSB–2
LSB+2 LSB+1 LSB
Figure 1. Right-Justified Mode
MSB MSB–1 MSB–2
LSB+2 LSB+1 LSB
L/RCLK
INPUT
BCLK
INPUT
SDATA
INPUT
L/RCLK
INPUT
BCLK
INPUT
SDATA
INPUT
L/RCLK
INPUT
BCLK
INPUT
SDATA
INPUT
L/RCLK
INPUT
BCLK
INPUT
SDATA
INPUT
LEFT CHANNEL
RIGHT CHANNEL
E MSB MSB–1 MSB–2
LSB+2 LSB+1 LSB
MSB MSB–1 MSB–2
Figure 2. I2S-Justified Mode
LSB+2 LSB+1 LSB
T LEFT CHANNEL
RIGHT CHANNEL
LE MSB MSB–1 MSB–2
LSB+2 LSB+1 LSB
MSB MSB–1 MSB–2
Figure 3. Left-Justified Mode
LSB+2 LSB+1 LSB
LEFT CHANNEL
RIGHT CHANNEL
SO MSB MSB–1
LSB+2 LSB+1 LSB
MSB MSB–1
LSB+2 LSB+1 LSB
Figure 4. Left-Justified DSP Mode
OB LEFT CHANNEL
RIGHT CHANNEL
MSB
MSB MSB–1
MSB MSB–1
LSB
MSB MSB–1 MSB–2
LSB+2 LSB+1 LSB
MSB MSB–1 MSB–2
Figure 5. 32 × FS Packed Mode
LSB+2 LSB+1 LSB
MSB MSB–1
–6–
REV. A