GS881Z32BD-133I Ver la hoja de datos (PDF) - Giga Semiconductor

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GS881Z32BD-133I

9Mb Pipelined and Flow Through Synchronous NBT SRAM

Giga Semiconductor 

GS881Z18B(T/D)/GS881Z32B(D)/GS881Z36B(T/D)

Sleep Mode

During normal operation, ZZ must be pulled low, either by the user or by it’s internal pull down resistor. When ZZ is pulled high,

the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to

low, the SRAM operates normally after ZZ recovery time.

Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of

Sleep mode is dictated by the length of time the ZZ is in a high state. After entering Sleep mode, all inputs except ZZ become

disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.

When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending

operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated

until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands

may be applied while the SRAM is recovering from Sleep mode.

Sleep Mode Timing Diagram

CK

tZZR

ZZ

Sleep

tZZS

tZZH

Designing for Compatibility

The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipelinemode via the FT signal found

on Pin 14. Not all vendors offer this option, however most mark Pin 14 as VDD or VDDQ on pipelined parts and VSS on flow

through parts. GSI NBT SRAMs are fully compatible with these sockets.

Pin 66, a No Connect (NC) on GSI’s GS8160Z18/36 NBT SRAM, the Parity Error open drain output on GSI’s GS881Z18/36B

NBT SRAM, is often marked as a power pin on other vendor’s NBT compatible SRAMs. Specifically, it is marked VDD or VDDQ

on pipelined parts and VSS on flow through parts. Users of GSI NBT devices who are not actually using the ByteSafe™ parity

feature may want to design the board site for the RAM with Pin 66 tied high through a 1k ohm resistor in Pipeline mode

applications or tied low in Flow Through mode applications in order to keep the option to use non-configurable devices open.

Rev: 1.00b 12/2002

16/37

© 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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