CL-PS7500FE Ver la hoja de datos (PDF) - Cirrus Logic

Número de pieza

componentes Descripción

Lista de partido

CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

2. PIN DESCRIPTIONS

This chapter gives the name, type, and relevant details of each of the CL-PS7500FE signals.

NOTE: When output signals are placed in the high-impedance state for long periods, ensure that they do not ‘float’

to an undefined logic level.

The following abbreiviations are used to indicate signal types.

IC

OCZ

IT

ICS

IA

OA

BTZ

TOD

CSOD

IAOD

Input, CMOS threshold

Output, CMOS levels, tristate

Input, TTL threshold

Input, CMOS Schmitt

Input, analog

Output, analog

Bidirectional, CMOS output, TTL threshold input level

Open-drain, TTL input

Open-drain, CMOS schmitt input

Input, analog with programmable internal pull-down transistor

For outputs and bidirectional signals, drive strength is classified 1, 2, or 3. See Chapter 22 for DC and AC

characteristics.

2.1 CL-PS7500FE Pin Descriptions

Name

LA[28:0]

LNBW

D[31:0]

SnA

Type

OCZ

OCZ

BTZ

IC

Drive

Strength

Description

2 LATCHED ADDRESS BUS: This bus is the latched version of the

ARM address for memory accesses, changing on the falling edge of

the internal MCLK signal.

2 LATCHED NOT BYTE WORD: This is a latched version of the inter-

nal NBW signal from the ARM processor, changing on the falling

edge of the internal MCLK signal.

2 DATA: The main data bus for the CL-PS7500FE. All external data

transfers happen through this bus. When the CL-PS7500FE is con-

figured for operation in 16-bit mode, only the lower 16 bits are used.

SYNCHRONOUS/NOT ASYNCHRONOUS: This pin is set accord-

ing to the relationship required between the internal clock signals,

MCLK and FCLK, for the ARM.

If this pin is set high, both the memory system and the CPU are

driven from the MEMCLK pin, and the required synchronous timing

relationship between the ARM processor clocks is generated auto-

matically on-chip. If different clocks are to be used for the MEMCLK

and CPUCLK inputs, the SnA pin must be set low.

June 1997

ADVANCE DATA BOOK v2.0

15

PIN DESCRIPTIONS

Share Link: