CL-PS7500FE-QC-A Ver la hoja de datos (PDF) - Cirrus Logic

Número de pieza

componentes Descripción

Lista de partido

CL-PS7500FE-QC-A

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

2.1 CL-PS7500FE Pin Descriptions (cont.)

Name

READY

nIORQ

nIOGT

nBLI

nBLO

nRBE

nWBE

nXIPMUX16

nXIPLATCH

nSIOCS1

nSIOCS2

nMSCS

nEASCS

nCCS

Type

IT

OCZ

IT

IT

OCZ

OCZ

OCZ

IT

IT

OCZ

OCZ

OCZ

OCZ

OCZ

Drive

Strength

Description

READY: This pin can stretch I/O accesses when set low during a

16-MHz PC-type I/O cycle.

2 I/O REQUEST: This signal is for the module-type I/O for handshak-

ing, together with nIOGT.

I/O GRANT: This signal is for the module-type I/O for handshaking,

together with nIORQ.

This input is used during module-type I/O reads to cause the latch-

ing of data from the BD port.

1 This signal is the latching signal for use with external latches on the

upper 16 bits of the external datapath to create a 32-bit-wide I/O

bus.

1 This active-low read enable is used to create a 32-bit-wide I/O bus

for an external transceiver attached to the upper 16 bits of the I/O

bus.

1 This active-low write enable is used to create a 32-bit-wide I/O bus

for an external transceiver attached to the upper 16 bits of the I/O

bus.

This signal is for XIP (execute in place) support. This signal multi-

plexes 16 bits of data from the upper or lower halfword of the

CL-PS7500FE internal data bus to the 16-bit I/O bus, depending on

its state during writes.

This signal is for XIP support and latches the upper 16 bits of data

from the I/O bus while the lower 16 bits are being read. This signal

is used in conjunction with nXIPMUX16 to enable XIP (for example,

from a 16-bit PCMCIA card).

1 This is the active-low chip select for simple I/O.

1 This is the active-low chip select for simple I/O, with address decode

modified according to the state of SETCS.

2 This is the active-low chip select for module-type I/O, with address

decode modified according to the state of SETCS.

1 This is the active-low chip select for extended 16-MHz PC-type I/O,

with address decode modified according to the state of SETCS.

1 NOT COMBO CHIP SELECT: This is the chip select signal for a PC

Combo chip.

20

PIN DESCRIPTIONS

ADVANCE DATA BOOK v2.0

June 1997

Share Link: