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CL-PS7500FE-56QC-A Datasheet PDF : 251 Pages
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CL-PS7500FE
System-on-a-Chip for Internet Appliance
6. ARM PROCESSOR MMU .................................................................................................... 38
6.1 MMU Program-Accessible Registers................................................................................................38
6.1.1 Translation Table Base Register ......................................................................................39
6.1.2 Domain Access Control Register......................................................................................39
6.1.3 Fault Status Register ........................................................................................................39
6.1.4 Fault Address Register .....................................................................................................39
6.2 Address Translation ..........................................................................................................................39
6.3 Translation Process ..........................................................................................................................40
6.3.1 TTB (Translation Table Base)............................................................................................40
6.3.2 Level One Fetch................................................................................................................40
6.3.3 Level One Descriptor ........................................................................................................41
6.3.4 Page Table Descriptor.......................................................................................................41
6.3.5 Section Descriptor ............................................................................................................42
6.4 Translating Section References ........................................................................................................42
6.4.1 Level Two Descriptor.........................................................................................................42
6.5 Translating Small Page References..................................................................................................44
6.6 Translating Large Page References .................................................................................................45
6.7 MMU Faults and CPU Aborts ...........................................................................................................47
6.8 Fault Address and Fault Status Registers (FAR, FSR).....................................................................47
6.9 Domain Access Control ....................................................................................................................48
6.10 Fault-Checking Sequence ................................................................................................................48
6.10.1 Alignment Fault.................................................................................................................49
6.10.2 Translation Fault................................................................................................................50
6.10.3 Domain Fault ....................................................................................................................50
6.10.4 Permission Fault ...............................................................................................................50
6.11 External Aborts.................................................................................................................................50
6.11.1 Interaction of the MMU, IDC, and Write Buffer..................................................................51
7. REGISTER DESCRIPTIONS................................................................................................ 52
7.1 Register Configuration......................................................................................................................52
7.1.1 Big and Little Endian (the Bigend Bit) ...............................................................................52
7.1.2 Configuration Bits for Backward Compatibility ..................................................................53
7.2 Operating Mode Selection ................................................................................................................54
7.3 Registers ..........................................................................................................................................55
7.3.1 PSRs (Program Status Registers) ....................................................................................56
7.4 Exceptions ........................................................................................................................................57
7.4.1 FIQ....................................................................................................................................57
7.4.2 IRQ ...................................................................................................................................58
7.4.3 Abort .................................................................................................................................58
7.4.4 Software Interrupt .............................................................................................................59
7.4.5 Undefined Instruction Trap ................................................................................................60
7.4.6 Vector Summary ...............................................................................................................60
7.4.7 Exception Priorities...........................................................................................................61
7.4.8 Interrupt Latencies............................................................................................................61
7.4.9 Reset ................................................................................................................................61
7.5 Configuration Control Registers .......................................................................................................62
7.5.1 Backward Compatibility ....................................................................................................62
7.5.2 Internal Coprocessor Instructions.....................................................................................62
7.5.3 Registers ..........................................................................................................................63
7.6 Register 1: Control (Write only) ........................................................................................................64
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TABLE OF CONTENTS
ADVANCE DATA BOOK v2.0
June 1997
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