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CL-PS7500FE Datasheet PDF : 251 Pages
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CL-PS7500FE
System-on-a-Chip for Internet Appliance
13. SOUND FEATURES ........................................................................................................... 133
13.1 Sound .............................................................................................................................................133
13.2 The Sound FIFO.............................................................................................................................133
13.3 The Digital Serial Sound Interface..................................................................................................133
13.3.1 Timing Formats...............................................................................................................133
14. VIDEO AND SOUND MACROCELL .................................................................................. 135
14.1 Features .........................................................................................................................................135
14.1.1 Flexible Video System ....................................................................................................135
14.1.2 Hardware Cursor ............................................................................................................135
14.1.3 Palette.............................................................................................................................135
14.1.4 Pixel Clock ......................................................................................................................136
14.1.5 Display Modes ................................................................................................................136
14.1.6 Power Management........................................................................................................136
14.1.7 On-chip Sound System...................................................................................................136
15. VIDEO MACROCELL INTERFACE.................................................................................... 138
15.1 Bus Interface ..................................................................................................................................138
15.2 Setting the FIFO Preload Value ......................................................................................................138
15.2.1 Example..........................................................................................................................139
16. THE VIDEO SOUND AND PROGRAMMER’S MODEL .................................................... 140
16.1 The Video and Sound Macrocell Registers ....................................................................................140
16.2 Video Palette: Address 0x0 ............................................................................................................142
16.3 Video Palette Address Pointer: Address 0x1 ..................................................................................142
16.4 LCD Offset Registers: Addresses 0x30 and 0x31 ..........................................................................143
16.5 Border Color Register: Address 0x4...............................................................................................144
16.6 Cursor Palette: Addresses 0x5–0x7 ...............................................................................................144
16.7 Horizontal Cycle Register (HCR): Address 0x80 ............................................................................145
16.8 Horizontal Sync Width Register (HSWR): Address 0x81................................................................145
16.9 Horizontal Border Start Register (HBSR): Address 0x82 ...............................................................145
16.10 Horizontal Display Start Register (HDSR): Address 0x83 ..............................................................146
16.11 Horizontal Display End Register (HDER): Address 0x84 ...............................................................146
16.12 Horizontal Border End Register (HBER): Address 0x85 ................................................................146
16.13 Horizontal Cursor Start Register (HCSR): Address 0x86 ...............................................................147
16.14 Horizontal Interlace Register (HIR): Address 0x87.........................................................................147
16.15 Horizontal Test Registers: Addresses 0x88 and 0x8H....................................................................147
16.16 Vertical Cycle Register (VCR): Address 0x90 ................................................................................147
16.17 Vertical Sync Width Register (VSWR): Address 0x91 ....................................................................148
16.18 Vertical Border Start Register (VBSR): Address 0x92....................................................................148
16.19 Vertical Display Start Register (VDSR): Address 0x93...................................................................148
16.20 Vertical Display End Register (VDER): Address 0x94 ....................................................................149
16.21 Vertical Border End Register (VBER): Address 0x95 .....................................................................149
16.22 Vertical Cursor Start Register (VCSR): Address 0x96....................................................................149
16.23 Vertical Cursor End Register (VCER): Address 0x97.....................................................................150
16.24 Vertical Test Registers: Addresses 0x98, 0x9A and 0x9C..............................................................150
16.25 External Register (EREG): Address 0xC........................................................................................151
16.26 Frequency Synthesizer Register (FSYNREG): Address 0xD .........................................................152
16.27 Control Register (CONREG): Address 0xE ....................................................................................153
16.28 Data Control Register (DCTL): Address 0xF ..................................................................................154
16.29 Sound Frequency Register (SFR): Address 0xB0 ..........................................................................154
16.30 Sound Control Register (SCTL): Address 0xB1 .............................................................................155
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TABLE OF CONTENTS
ADVANCE DATA BOOK v2.0
June 1997
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