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DS2141A

T1 Controller

Dallas Semiconductor -> Maxim Integrated 

RFDL: RECEIVE FDL REGISTER (28h)

(MSB)

RFDL7

RFDL6

RFDL5

RFDL4

RFDL3

RFDL2

SYMBOL

RFDL7

RFDL0

POSITION

RFDL.7

RFDL.0

NAME AND DESCRIPTION

MSB of the Received FDL Code.

LSB of the Received FDL Code.

RFDL1

DS2141A

(LSB)

RFDL0

The Receive FDL Register (RFDL) reports the incoming

Facility Data Link (FDL) or the incoming Fs–bits. The

LSB is received first.

RFDLM1: RECEIVE FDL MATCH REGISTER 1 (29h)

RFDLM2: RECEIVE FDL MATCH REGISTER 2 (2Ah)

(MSB)

RFDL7

RFDL6

RFDL5

RFDL4

RFDL3

RFDL2

SYMBOL

RFDL7

RFDL0

POSITION

RFDL.7

RFDL.0

NAME AND DESCRIPTION

MSB of the FDL Match Code.

LSB of the FDL Match Code.

RFDL1

(LSB)

RFDL0

When the byte in the Receive FDL Register matches ei-

ther of the two Receive FDL Match Registers

(RFDLM1/RFDLM2), RSR2.2 will be set to a 1 and the

INT2 will go active if enabled via IMR2.2.

6.2 TRANSMIT SECTION

The transmit section will shift out either the FDL (in the

ESF framing mode) or the Fs–bits (in the D4 framing

mode) contained in the Transmit FDL register (TFDL)

into the T1 data stream. When a new value is written to

the TFDL, it will be multiplexed serially (LSB first) into

the proper position in the outgoing T1 data stream. After

the full eight bits have been shifted out, the DS2141A

will signal the host microcontroller that the buffer is

empty and that more data is needed by setting the

SR2.3 bit to a 1. The INT2 will also toggle low if enabled

via IMR2.3. The user has 2 ms (1.5 ms in SLC–96 ap-

plications) to update the TFDL with a new value. If the

TFDL is not updated, the old value in the TFDL will be

transmitted once again.

The DS2141A also contains a zero stuffer which is con-

trolled via the CCR2.4 bit. In both ANSI T1.403 and

TR54016, communications on the FDL follows a subset

of a LAPD protocol. The LAPD protocol states that no

more than five 1s should be transmitted in a row so that

the data does not resemble an opening or closing flag

(01111110) or an abort signal (11111111). If enabled via

CCR2.4, the DS2141A will automatically look for five 1s

in a row. If it finds such a pattern, it will automatically in-

sert a 0 after the five 1s. The CCR2.0 bit should always

be set to a 1 when the DS2141A is inserting the FDL.

More on how to use the DS2141A in FDL applications is

covered in a separate Application Note.

022698 17/35

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