CS62180B-IP Ver la hoja de datos (PDF) - Cirrus Logic

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CS62180B-IP

T1 Framer

Cirrus Logic 

CS62180A

CS62180B

Frame X 11 12 13 14 15 16 17 18 19 20 21 22

Data Link

C1 C2 C3 C4 C5 C6

TMSYNC

TFSYNC

TMO

TSIGSEL

TSIGFR

B

A

TLCLK

44 45 46 47 48 49 50 51 52 53 54 55 56 57 58

M3 A1 A2 S1 S2 S3 S4

B

A

72 1 2 3

B

Figure 8. SLC-96® Multiframe Transmit Timing

Frame X 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9

TMSYNC

TFSYNC

TMO

TLCLK

TSIGSEL

TSIGFR

Figure 9. T1DM Multiframe Transmit Timing

T1DM Timing

Frame and multiframe timing is output on

TCHCLK, TMO, and TLCLK. TMO transitions

high at the beginning of every superframe (50%

duty cycle). TSIGFR goes high during signaling

frames (every 6 frames).

The channel 24 data link is input on TLINK us-

ing TLCLK. TLCLK is a 8 kHz clock with a

duty cycle of 1 bit period high per frame. When

TLCLK is high, TLINK will be sampled on the

falling edge of TCLK. See Figure 9 and

"Switching Characteristics - Transmitter" for tim-

ing diagrams.

TSIGSEL and TSIGFR serve no purpose in the

T1DM mode and can be ignored. However,

TSIGSEL and TSIGFR operate as in 193S

mode.

DS225PP1

15

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