DS2175 Ver la hoja de datos (PDF) - Dallas Semiconductor -> Maxim Integrated

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DS2175

T1/CEPT Elastic Store

Dallas Semiconductor -> Maxim Integrated 

DS2175

PIN DESCRIPTION Table 1

PIN SYMBOL

TYPE

DESCRIPTION

1 RCLKSEL

I Receive Clock Select. Tie to VSS for 1.544 MHz applications, to VDD

for 2.048 MHz.

2 RCLK

I Receive Clock. 1.544 or 2.048 MHz data clock.

3 RSER

I Receive Serial Data. Sampled on falling edge of RCLK.

4 RMSYNC

I Receive Multifram Sync. Rising edge establishes receive side frame and

multiframe boundaries.

5 FSD

O Frame Slip Direction. State indicates direction of last slip; latched on slip

occurrence.

6 SLIP

O Frame Slip. Active low, open collector output. Held low for 65 SYSCLK

cycles when a slip occurs.

7 ALN

I Align. Recenters buffer on next system side frame boundary when forced

low; negative edge–triggered.

8

VSS

9 SCLKSEL

– Signal Ground. 0.0 volts

I System Clock Select. Tie to VSS for 1.544 MHz applications, to VDD for

2.048 MHz.

10 S/P

11 SCHCLK

I Serial/Parallel Select. Tie to VSS for parallel backplane applications, to

VDD for serial.

O System Channel Clock. Transitions high on channel boundaries; useful

for serial to parallel conversion of channel data.

12 SFSYNC

I System Frame Sync. Rising edge establishes system side frame bound-

aries.

13 SMSYNC

O System Multiframe Sync. Slip–compensated multiframe output; used

with RMSYNC to monitor depth of store real time.

14 SSER

O System Serial Data. Updated on rising edge of SYSCLK.

15 SYSCLK

I System Clock. 1.544 or 2.048 MHz data clock.

16 VDD

– Positive Supply. 5.0 volts.

022798 3/12

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