CXD2412AQ Ver la hoja de datos (PDF) - Sony Semiconductor

Número de pieza

componentes Descripción

Lista de partido

CXD2412AQ

Timing Generator for LCD Panels

Sony Semiconductor 

CXD2412AQ

Vertical Output

The vertical display position is varied as shown below.

VP1 VP2

L

L

H

L

L

H

H

H

After 2H

After 1H

Central value

1H before

LCD Panel AC Driving for No Signal

With no signal, also, provision is made as follows for AC driving of the LCD panel.

Horizontal pulses The PLL is set to the free-running state.

Therefore, the horizontal pulse frequency depends on the PLL free-running frequency.

Vertical pulses

The number of lines is counted by an internal counter, and VST and FRP are output in a

specific cycle.

VST Cycle with No Signal

SLAUX = L

NTSC

NTSC-WIDE

MNDC

PAL

PAL+

HD

545H

641H

577H

SLAUX = H

All modes

769H

Note) This TG determines there to be no signal if there is no VSYNC input during the above cycle.

– 18 –

Share Link: