PI74SSTV16857A Ver la hoja de datos (PDF) - Pericom Semiconductor
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PI74SSTV16857A Datasheet PDF : 6 Pages
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PI74SSTV16857
14-Bit Registered Buffer 1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122
Timing Requirements (over recommended operating free-air temperature range, unless otherwise noted)
VDD = 2.5V ±0.2V
Min.
Max.
Units
fclock
Clock frequency
tPD
Clock to output time
tRST
Reset to output time
tSL
Output slew rate
Setup time, fast slew rate(5,7)
tsu
Setup time, slow slew rate(6,7)
Hold time, fast slew rate(5,7)
th
Hold time, slow slew rate(6,7)
Data before CK↑, CK↓
Data after CK↑, CK↓
170
MHz
TBD
TBD
ns
5
1
4
V/ns
0.75
0.9
ns
0.75
0.9
Notes: 5. For data signal input slew rate ≥1V/ns.
6. For data signal input slew rate ≥0.5V/ns and <1V/ns.
7. CLK, CLK signals input slew rates are ≥1V/ns.
Switching characteristics (over recommended operating free-air temperature range, unless otherwise noted.)
(See test circuits and switching waveforms).
Parameter
fmax
tpd
tphl
From
(Input)
CLK, CLK
RESET
To
(Output)
Q
Q
Min.
170
1.1
VDD = 2.5V ±0.2V
Typ.
Max.
2.8
5.0
Units
MHz
ns
PS8460C 06/04/01
4
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