PI74SSTV16857K Ver la hoja de datos (PDF) - Pericom Semiconductor
Número de pieza
componentes Descripción
Lista de partido
PI74SSTV16857K Datasheet PDF : 6 Pages
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PI74SSTV16857
14-Bit Registered Buffer 1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122
Test Circuit and Switching Waveforms
LVRCEMInSOpEuSTt
IDD(9)
Input
VDD/2
VDD
0V
tinact
tact
90% IDDH
10%
IDDL
Voltage and Current Waveforms
Input Active and Inactive Times
tw
VREF
VIH
VREF
VIL
Voltage Waveforms - Pulse Duration
From Output
Under Test
VTT
RL = 50Ω
TEST POINT
CL = 30pF(8)
Load Circuit
Timing
Input
VICR
VICR
VI(PP)
Output
t PLH
VTT
t PHL
VTT
VOH
VOL
Voltage Waveforms - Propagation Delay Times
Timing
Input
VICR
VI(PP)
Input
tsu
VREF
th
VREF
VIH
VIL
Voltage Waveforms - Setup and Hold Times
LVCMOS
RESET
Input
Output
VDD/2
t PHL
VIH
VTT
VIL
VOH
VOL
Voltage Waveforms - Propagation Delay Times
Parameter Measurement Information (VDD = 2.5V ±0.2V)
Notes:
8. CL includes probe and jig capacitance.
9. IDD tested with clock and data inputs held at VDD or GND, and IO = 0mA.
10. All input pulses are supplied by generators having the following characteristics:
PRR ≤10 MHz, ZO = 50Ω. Input slew rate = 1V/ns ±20% (unless otherwise specified).
11. The outputs are measured one at a time with one transition per measurement.
12. VTT = VREF = VDDQ/2
13. VIH = VREF + 350mV (ac voltage levels) for SSTL inputs. VIH = VDD for LVCMOS input.
14. VIL = VREF + 350mV (ac voltage levels) for SSTL inputs. VIL = GND for LVCMOS input.
15. tPLH and tPHL are the same as tpd.
5
PS8460C 06/04/01
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