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HI5905IN

14-Bit, 5MSPS A/D Converter

Intersil 

HI5905

TABLE 1. A/D CODE TABLE

DIFFERENTIAL

TWO’S COMPLEMENT BINARY OUTPUT CODE

INPUT

VOLTAGE † MSB

LSB

CODE

(USING

CENTER

INTERNAL

DESCRIPTION REFERENCE) D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

+Full Scale

(+FS) - 1/4 LSB

+1.99994V

0

1

1

1

1

1

1

1

1

1

1

1

1

1

+FS - 1 1/4 LSB 1.99969V

0

1

1

1

1

1

1

1

1

1

1

1

1

0

+ 3/4 LSB

183.105µV

0

0

0

0

0

0

0

0

0

0

0

0

0

0

- 1/4 LSB

-61.035µV

1

1

1

1

1

1

1

1

1

1

1

1

1

1

-FS + 1 3/4 LSB -1.99957V

1

0

0

0

0

0

0

0

0

0

0

0

0

1

-Full Scale

(-FS) + 3/4 LSB

-1.99982V

1

0

0

0

0

0

0

0

0

0

0

0

0

0

† The voltages listed above represent the ideal center of each two’s complement binary output code shown.

Analog Input, Single-Ended Connection

The configuration shown in Figure 11 may be used with a

single ended AC coupled input. Sufficient headroom must be

provided such that the input voltage never goes above +5V

or below AGND .

VIN

VIN+

VIN

VDC

VDC

VIN+

R

C

HI5905

VIN -

VDC

HI5905

VIN-

FIGURE 11. AC COUPLED SINGLE ENDED INPUT

Again, the difference between the two internal voltage

references is 2V. If VIN is a 4VP-P sinewave, then VIN+ is a

4VP-P sinewave riding on a positive voltage equal to VDC. The

converter will be at positive full scale when VIN+ is at VDC + 2V

(VIN+ - VIN- = 2V) and will be at negative full scale when VIN+

is equal to VDC - 2V (VIN+ - VIN- = -2V). In this case, VDC

could range between 2V and 3V without a significant change in

ADC performance. The simplest way to produce VDC is to use

the VDC bias voltage output of the HI5905.

The single ended analog input can be DC coupled (Figure

12) as long as the input is within the analog input common

mode voltage range.

FIGURE 12. DC COUPLED SINGLE ENDED INPUT

The resistor, R, in Figure 12 is not absolutely necessary but

may be used as a load setting resistor. A capacitor, C,

connected from VIN+ to VIN- will help filter any high

frequency noise on the inputs, also improving performance.

Values around 20pF are sufficient and can be used on AC

coupled inputs as well. Note, however, that the value of

capacitor C chosen must take into account the highest

frequency component of the analog input signal.

A single ended source will give better overall system

performance if it is first converted to differential before

driving the HI5905.

Digital I/O and Clock Requirements

The HI5905 provides a standard high-speed interface to

external TTL/CMOS logic families. The digital CMOS clock

input has TTL level thresholds. The low input bias current

allows the HI5905 to be driven by CMOS logic. The digital

CMOS outputs have a separate +5.0V digital supply input pin.

In order to ensure rated performance of the HI5905, the duty

cycle of the clock should be held at 50% ±5%. It must also

have low jitter and operate at standard TTL levels.

Performance of the HI5905 will only be guaranteed at

conversion rates above 0.5MSPS. This ensures proper

performance of the internal dynamic circuits.

9

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