AD7890(RevA) Ver la hoja de datos (PDF) - Analog Devices
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AD7890 Datasheet PDF : 20 Pages
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AD7890
In the external clocking mode, it is possible to write data to the
Control Register or read data from the output register while a
conversion is in progress. The same data is presented in Figure
18 as in Figure 17 except that in this case the output data read
for the device occurs during conversion. These results are
achieved with a serial clock rate of 2.5 MHz. If a higher serial
clock rate is used, the code transition noise will degrade from
that shown in the plot of Figure 18. This has the effect of inject-
ing noise onto the die while bit decisions are being made and
this increases the noise generated by the AD7890. The histo-
gram plot for 8192 conversions of the same dc input now shows
a larger spread of codes with the rms noise for the AD7890-2
increasing to 170 µV. This effect will vary depending on where
the serial clock edges appear with respect to the bit trials of the
conversion process. It is possible to achieve the same level of
performance when reading during conversion as when reading
after conversion depending on the relationship of the serial clock
edges to the bit trial points (i.e., the relationship of the serial
clock edges to the CLK IN edges). The bit decision points
on the AD7890 are on the falling edges of the master clock
(CLK IN) during the conversion process. Clocking out new
data bits at these points (i.e. the rising edge of SCLK) is the
most critical from a noise standpoint. The most critical bit deci-
sions are the MSBs, so to achieve the level of performance out-
lined in Figure 18, reading within 1 µs after the rising edge of
CONVST should be avoided.
8000
7000
6000
SAMPLING FREQUENCY =
102.4kHz
TA = +25°C
5000
4000
3000
2000
1000
0
(X–4) (X–3) (X–2) (X–1) X (X+1) (X+2) (X+3) (X+4)
CODE
Figure 18. Histogram of 8192 Conversions with Read
During Conversion
Writing data to the Control Register also has the effect of intro-
ducing digital activity onto the part while conversion is in
progress. However, since there are no output drivers active dur-
ing a write operation, the amount of current flowing on the die
is less than for a read operation. Therefore, the amount of noise
injected into the die is less than for a read operation. Figure 19
shows the effect of a write operation during conversion. The his-
togram plot for 8192 conversions of the same dc input now
shows a larger spread of codes than for ideal conditions but
smaller than for a read operation. The resulting rms noise for
the AD7890-2 is 110 µV. In this case, the serial clock frequency
was 10 MHz.
8000
7000
6000
SAMPLING FREQUENCY =
102.4kHz
TA = +25°C
5000
4000
3000
2000
1000
0
(X–4) (X–3) (X–2) (X–1) X (X+1) (X+2) (X+3) (X+4)
CODE
Figure 19. Histogram of 8192 Conversions with Write
During Conversion
Dynamic Performance
The AD7890 contains an on-chip track/hold, allowing the part
to sample input signals up to 50 kHz on any of its input chan-
nels. Many of the AD7890’s applications will simply require it
to sequence through low frequency input signals across its eight
channels. There may be some applications, however, for which
the dynamic performance of the converter out to 40 kHz input
frequency is of interest. It is recommended for these wider band
sampling applications that the hardware conversion start method
is used for reasons outlined previously.
These applications require information on the ADC’s effect on
the spectral content of the input signal. Signal to (Noise +
Distortion), total harmonic distortion, peak harmonic or spuri-
ous and intermodulation distortion are all specified. Figure 20
shows a typical FFT plot of a 10 kHz, 0 V to +2.5 V input after
being digitized by the AD7890-2 operating at a 102.4 kHz sam-
pling rate. The signal to (Noise + Distortion) is 71.5 dB and the
total harmonic distortion is –85 dB. It should be noted that
reading data from the part during conversion at 10 MHz serial
clock does have a significant impact on dynamic performance.
Therefore, for sampling applications, it is recommended not to
read data during conversion.
0
F = /2
SAMPLE RATE = 102.4 kHz
INPUT FREQUENCY = 10 kHz
–30
SNR = 71.5 dB
TA = +25°C
–60
–90
–120
0
25.6
51.2
FREQUENCY – kHz
SNR IS SIGNAL TO (NOISE + DISTORTION) RATIO.
Figure 20. AD7890 FFT Plot
–18–
REV. A
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