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EP7209-CB-A

Ultra-Low-Power Audio Decoder System-on-Chip

Cirrus Logic 

EP7209

5.13 ‘End Of Interrupt’ Locations ............................................................................................ 81

5.13.1 BLEOI Battery Low End of Interrupt ...................................................................... 81

5.13.2 MCEOI Media Changed End of Interrupt .............................................................. 81

5.13.3 TEOI Tick End of Interrupt Location ...................................................................... 81

5.13.4 TC1EOI TC1 End of Interrupt Location ................................................................. 81

5.13.5 TC2EOI TC2 End of Interrupt Location ................................................................. 82

5.13.6 RTCEOI RTC Match End of Interrupt .................................................................... 82

5.13.7 UMSEOI UART1 Modem Status Changed End of Interrupt .................................. 82

5.13.8 COEOI Codec End of Interrupt Location ............................................................... 82

5.13.9 KBDEOI Keyboard End of Interrupt Location ........................................................ 82

5.13.10 SRXEOF End of Interrupt Location ..................................................................... 82

5.14 State Control Registers ................................................................................................... 82

5.14.1 STDBY Enter the Standby State Location ............................................................. 82

5.14.2 HALT Enter the Idle State Location ....................................................................... 82

5.15 SS2 Registers ................................................................................................................. 83

5.15.1 SS2DR Synchronous Serial Interface 2 Data Register ......................................... 83

5.15.2 SS2POP Synchronous Serial Interface 2 Pop Residual Byte ............................... 83

5.16 DAI Register Definitions .................................................................................................. 83

5.16.1 DAI Control Register ............................................................................................. 84

5.16.1.1 DAI Enable (DAIEN) .................................................................................. 85

5.16.1.2 DAI Interrupt Generation ........................................................................... 85

5.16.1.3 Left Channel Transmit FIFO Interrupt Mask (LCTM) ................................. 85

5.16.1.4 Left Channel Receive FIFO Interrupt Mask (LARM) ................................. 85

5.16.1.5 Right Channel Transmit FIFO Interrupt Mask (RCTM) .............................. 86

5.16.1.6 Right Channel Receive FIFO Interrupt Mask (RCRM) .............................. 86

5.16.1.7 Loop Back Mode (LBM) ............................................................................. 86

5.16.2 DAI Data Registers ................................................................................................ 87

5.16.2.1 DAI Data Register 0 .................................................................................. 87

5.16.2.2 DAI Data Register 1 .................................................................................. 88

5.16.2.3 DAI Data Register 2 .................................................................................. 88

5.16.3 DAI Status Register ............................................................................................... 89

5.16.3.1 Right Channel Transmit FIFO Service Request Flag (RCTS) ................... 89

5.16.3.2 Right Channel Receive FIFO Service Request Flag (RCRS) ................... 89

5.16.3.3 Left Channel Transmit FIFO Service Request Flag (LCTS) ...................... 89

5.16.3.4 Left Channel Receive FIFO Service Request Flag (LCRS) ...................... 90

5.16.3.5 Right Channel Transmit FIFO Underrun Status (RCTU) ........................... 90

5.16.3.6 Right Channel Receive FIFO Overrun Status (RCRO) ............................. 90

5.16.3.7 Left Channel Transmit FIFO Underrun Status (LCTU) .............................. 90

5.16.3.8 Left Channel Receive FIFO Overrun Status (LCRO) ................................ 90

5.16.3.9 Right Channel Transmit FIFO Not Full Flag (RCNF) ................................. 90

5.16.3.10 Right Channel Receive FIFO Not Empty Flag (RCNE) ........................... 90

5.16.3.11 Left Channel Transmit FIFO Not Full Flag (LCNF) .................................. 91

5.16.3.12 Left Channel Receive FIFO Not Empty Flag (LCNE) .............................. 91

5.16.3.13 FIFO Operation Completed Flag (FIFO) ................................................. 91

6. ELECTRICAL SPECIFICATIONS .......................................................................................... 93

6.1 Absolute Maximum Ratings .............................................................................................. 93

6.2 Recommended Operating Conditions .............................................................................. 93

6.3 DC Characteristics ............................................................................................................ 93

6.4 AC Characteristics ............................................................................................................ 95

6.5 I/O Buffer Characteristics ................................................................................................ 102

6.6 JTAG Bandary Scan Signal Ordering ............................................................................. 102

7. TEST MODES ....................................................................................................................... 106

7.1 Oscillator and PLL Bypass Mode .................................................................................... 106

7.2 Oscillator and PLL Test Mode ......................................................................................... 106

DS453PP2

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