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ISP1581 Datasheet PDF : 80 Pages
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Philips Semiconductors
ISP1581
USB 2.0 HS interface device
8. Modes of operation
The ISP1581 has two bus configuration modes, selected via pin BUS_CONF/DA0 at
power-up:
Split Bus mode (BUS_CONF = 0): 8-bit multiplexed address/data bus and
separate 8-bit/16-bit DMA bus
Generic Processor mode (BUS_CONF = 1); separate 8-bit address and 16-bit
data bus
Details of the bus configurations for each mode are given in Table 3. Typical interface
circuits for each mode are given in Section 14.
Table 3: Bus configuration modes
BUS_CONF PIO width
DMA width
Description
DMAWD = 0 DMAWD = 1
0
AD[7:0]
D[7:0]
D[15:0] Split Bus mode: multiplexed address/data on pins AD[7:0];
separate 8/16-bit DMA bus on pins DATA[15:0]
1
A[7:0]
D[7:0]
D[15:0] Generic Processor mode: separate 8-bit address on pins
D[15:0]
AD[7:0]; 16-bit data (PIO and DMA) on pins DATA[15:0]
9. Register descriptions
Table 4: Register summary
Name
Destination
Initialization registers
Address
Mode
device
device
Interrupt Configuration
device
Interrupt Enable
DMA Configuration
DMA Hardware
Data flow registers
Endpoint Index
Control Function
Data Port
Buffer Length
Endpoint MaxPacketSize
Endpoint Type
device
DMA controller
DMA controller
endpoints
endpoint
endpoint
endpoint
endpoint
endpoint
Short Packet
endpoint
Address
(Hex)
Description
Size
(bytes)
00
USB device address + enable
1
0C
power-down options, global interrupt
1
enable, SoftConnect
10
interrupt sources, trigger mode, output 1
polarity
14
interrupt source enabling
4
38
see sub-section “DMA registers”
2
3C
see sub-section “DMA registers”
1
2C
endpoint selection, data flow direction
1
28
endpoint buffer management
1
20
data access to endpoint FIFO
2
1C
packet size counter
2
04
maximum packet size
2
08
selects endpoint type: control,
2
isochronous, bulk or interrupt
24
short packet received on OUT endpoint 2
9397 750 09665
Product data
Rev. 04 — 18 July 2002
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
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