ISP1581 Ver la hoja de datos (PDF) - Philips Electronics

Número de pieza

componentes Descripción

fabricante

ISP1581

Universal serial bus 2.0 high-speed interface device

Philips Electronics 

Philips Semiconductors

ISP1581

USB 2.0 HS interface device

9.2.2 Mode register (address: 0CH)

This register consists of 1 byte (bit allocation: see Table 7). In 16-bit bus mode the

upper byte is ignored.

The Mode register controls the resume, suspend and wake-up behavior, interrupt

activity, soft reset, clock signals and SoftConnect operation.

Table 7: Mode register: bit allocation

Bit

7

6

5

Symbol

CLKAON SNDRSU GOSUSP

Reset

0

0

0

Bus reset

0

0

0

Access

R/W

R/W

R/W

4

SFRESET

0

0

R/W

3

GLINTENA

0

unchanged

R/W

2

WKUPCS

0

0

R/W

1

reserved

-

-

-

0

SOFTCT

0

unchanged

R/W

Table 8:

Bit

7

6

5

4

3

2

1

0

Mode register: bit description

Symbol

Description

CLKAON

Clock Always On: A logic 1 indicates that the internal clocks

are always running even during ‘suspend’ state. A logic 0

switches off the internal oscillator and PLL, when they are not

needed. During ‘suspend’ state, this bit must be set to logic 0 to

meet the suspend current requirements. The clock is stopped

after a delay of approximately 2 ms, following the setting of bit

GOSUSP.

SNDRSU

Send Resume: Writing a logic 1 followed by a logic 0 will

generate an upstream ‘resume’ signal of 10 ms duration, after a

5 ms delay.

GOSUSP

Go Suspend: Writing a logic 1 followed by a logic 0 will activate

‘suspend’ mode.

SFRESET

Soft Reset: Writing a logic 1 followed by a logic 0 will enable a

software-initiated reset to ISP1581. A soft reset is similar to a

hardware-initiated reset (via the RESET pin).

GLINTENA

Global Interrupt Enable: A logic 1 enables all interrupts.

Individual interrupts can be masked OFF by clearing the

corresponding bits in the Interrupt Enable register. Bus reset

value: unchanged.

WKUPCS

Wake-up on Chip Select: A logic 1 enables remote wake-up

via a LOW level on input CS.

-

reserved; must write logic 0

SOFTCT

SoftConnect: A logic 1 enables the connection of the 1.5 kΩ

pull-up resistor on pin RPU to the D+ line. Bus reset value:

unchanged.

9.2.3 Interrupt Configuration register (address: 10H)

This 1-byte register determines the behavior and polarity of the INT output. The bit

allocation is shown in Table 9. When the USB SIE receives or generates a ACK, NAK

or STALL, it will generate interrupts depending on three Debug mode bit fields:

• CDBGMOD[1:0]: interrupts for the Control endpoint 0

• DDBGMODIN[1:0]: interrupts for the DATA IN endpoints 1 to 7

9397 750 09665

Product data

Rev. 04 — 18 July 2002

© Koninklijke Philips Electronics N.V. 2002. All rights reserved.

18 of 80

Share Link: