74AC191CW Ver la hoja de datos (PDF) - Fairchild Semiconductor
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74AC191CW Datasheet PDF : 10 Pages
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RC Truth Table
Inputs
PL
CE
TC
CP
H
L
(Note 1)
H
H
H
X
X
H
X
L
X
L
X
X
X
Outputs
RC
H
H
H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Transition
= Clock Pulse
Note 1: TC is generated internally
Functional Description
The AC191 is a synchronous up/down counter. The AC191
is organized as a 4-bit binary counter. It contains four edge-
triggered flip-flops with internal gating and steering logic to
provide individual preset, count-up and count-down opera-
tions.
Each circuit has an asynchronous parallel load capability
permitting the counter to be preset to any desired number.
When the Parallel Load (PL) input is LOW, information
present on the Parallel Load inputs (P0–P3) is loaded into
the counter and appears on the Q outputs. This operation
overrides the counting functions, as indicated in the Mode
Select Table.
A HIGH signal on the CE input inhibits counting. When CE
is LOW, internal state changes are initiated synchronously
by the LOW-to-HIGH transition of the clock input. The
direction of counting is determined by the U/D input signal,
as indicated in the Mode Select Table. CE and U/D can be
changed with the clock in either state, provided only that
the recommended setup and hold times are observed.
Two types of outputs are provided as overflow/underflow
indicators. The terminal count (TC) output is normally
LOW. It goes HIGH when the circuits reach zero in the
count down mode or 15 in the count up mode. The TC out-
put will then remain HIGH until a state change occurs,
whether by counting or presetting or until U/D is changed.
The TC output should not be used as a clock signal
because it is subject to decoding spikes.
The TC signal is also used internally to enable the Ripple
Clock (RC) output. The RC output is normally HIGH. When
CE is LOW and TC is HIGH, RC output will go LOW when
the clock next goes LOW and will stay LOW until the clock
goes HIGH again. This feature simplifies the design of mul-
tistage counters, as indicated in Figure 1 and Figure 2. In
Figure 1, each RC output is used as the clock input for the
next higher stage. This configuration is particularly advan-
tageous when the clock source has a limited drive capabil-
ity, since it drives only the first stage. To prevent counting in
all stages it is only necessary to inhibit the first stage, since
a HIGH signal on CE inhibits the RC output pulse, as indi-
cated in the RC Truth Table. A disadvantage of this config-
uration, in some applications, is the timing skew between
state changes in the first and last stages. This represents
the cumulative delay of the clock as it ripples through the
preceding stages.
A method of causing state changes to occur simulta-
neously in all stages is shown in Figure 2. All clock inputs
are driven in parallel and the RC outputs propagate the
carry/borrow signals in ripple fashion. In this configuration
the LOW state duration of the clock must be long enough to
allow the negative-going edge of the carry/borrow signal to
ripple through to the last stage before the clock goes HIGH.
There is no such restriction on the HIGH state duration of
the clock, since the RC output of any device goes HIGH
shortly after its CP input goes HIGH.
The configuration shown in Figure 3 avoids ripple delays
and their associated restrictions. The CE input for a given
stage is formed by combining the TC signals from all the
preceding stages. Note that in order to inhibit counting an
enable signal must be included in each carry gate. The
simple inhibit scheme of Figure 1 and Figure 2 doesn't
apply, because the TC output of a given stage is not
affected by its own CE.
Mode Select Table
Inputs
PL CE U/D
H
L
L
H
L
H
L
X
X
H
H
X
State Diagram
Mode
CP
Count Up
Count Down
X Preset (Asyn.)
X No Change (Hold)
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