BS62LV2001STC-70 Ver la hoja de datos (PDF) - Brilliance Semiconductor
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BS62LV2001STC-70 Datasheet PDF : 10 Pages
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BSI
BS62LV2001
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
Vcc/0V
5ns
0.5Vcc
AC TEST LOADS AND WAVEFORMS
3.3V
OUTPUT
1269 Ω
3.3V
OUTPUT
1269 Ω
INCLUDING
JIG AND
SCOPE
100PF
1404 Ω
INCLUDING
JIG AND
SCOPE
5PF
1404 Ω
FIGURE 1A
FIGURE 1B
OUTPUT
THEVENIN EQUIVALENT
667 Ω
1.73V
ALL INPUT PULSES
Vcc
GND
10%
→
90% 90%
←
→
FIGURE 2
10%
← 5ns
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
MAY CHANGE
FROM L TO H
,
DON T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
OUTPUTS
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
WILL BE
CHANGE
FROM L TO H
CHANGE :
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
AC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC, Vcc = 3.0V )
READ CYCLE
JEDEC
PARAMETER
NAME
t
AVAX
t
AVQV
t
E1LQV
t
E2HOV
t
GLQV
t
E1LQX
t
E2HOX
t
GLQX
t
E1HQZ
t
E2HQZ
t
GHQZ
PARAMETER
NAME
t
RC
t
AA
t
ACS1
t
ACS2
t
OE
t
CLZ1
t
CLZ2
t
OLZ
t
CHZ1
t
CHZ1
t
OHZ
DESCRIPTION
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Chip Select to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Chip Deselect to Output in High Z
Output Disable to Output in High Z
(CE1)
(CE2)
(CE1)
(CE2)
(CE1)
(CE2)
BS62LV2001-70
MIN. TYP. MAX.
70
--
--
--
--
70
--
--
70
--
--
70
--
--
35
10
--
--
10
--
--
10
--
--
0
--
35
0
--
35
0
--
30
t
AXOX
t
OH
Output Disable to Output Address Change
10
--
--
BS62LV2001-10
MIN. TYP. MAX.
100 --
--
--
-- 100
--
-- 100
--
-- 100
--
--
50
15
--
--
15
--
--
15
--
--
0
--
40
0
--
40
0
--
35
15
--
--
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
R0201-BS62LV2001
4
Revision 2.5
April 2002
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