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GDC21D401B

Video Decoder

Hyundai Micro Electronics 

5.3 STC (System Time Clock)

Generation

Internal STC counter is supported. STC value

should be loaded after the reset by host

microprocessor or transport decoder, and be

counted at 90 KHz clock derived from external 27

MHz system clock. Also it should be loaded

whenever the system time base is changed. 27

MHz system clock is supplied by transport

decoder through external 27 MHz clock input.

5.4 DTS (Decoding Time Stamp)

Synchronization

The DTS values are determined when the

associated pictures are decoded referring to the

STC. The transport decoder must extract PTS &

DTS values from MPEG-2 system layer, and

transfer them to the VD through host interface or

transport data interface. DTS values are extracted

and stored in DTS-FIFO with 8-bit associated

picture numbers(they are defined by the VD

internally).

Before each picture decoding, picture decoding

controller checks if there is a DTS associated with

each picture. And it compares the DTS value from

DTS-FIFO with STC value.

The DTS value is considered to match the current

STC value if the DTS satisfies this equation:

STC + jitter_b(negative) < DTS < STC + jitter_f(positive)

In the case that jitter is the tolerance for the

comparison:

If the DTS is less than STC + jitter_b (in

other words, the time for current picture

decoding has already passed), picture

decoding controller discards B picture in

VBV delay mode and any picture in low

delay mode without decoding it.

If the DTS is greater than STC + jitter_f (the

time for current picture decoding has not

come yet), picture decoding controller pauses

decoding process until the DTS value falls

within the allowed tolerance of STC.

GDC21D401B

When system time base is changed, the time base

of the current DTS can differ from that of the new

STC temporarily because of video decoding delay.

In this case, for about 0.5 sec, DTS

synchronization mode must be disabled by using

decoding mode register.

5.5 Error Concealment

When the VLD detects a bitstream syntax error or

an MPEG-2 error code (0x000001B4), it performs

appropriate error handling and error concealment

to continue the decoding and to minimize the

effect of the error on decoded video. If an error

occurs at picture data layer, the slice-based error

concealment is performed. If an error occurs at

header layer, the associated sequence is skipped.

5.6 User Data Read

User data in MPEG Video Sequence can be read

through host interface(I2C) as follows. If user data

interrupt is enabled, user data is stored in internal

user data FIFO, and once ‘PIC_DEC_SYNC’ is

set to ‘high’, a interrupt signal is generated which

informs host that user data is stored in user data

FIFO. If user data interrupt is disabled, user data

is discarded.

When user data interrupt signal is generated, host

reads the ‘U_D_COUNT’ register for bytes of

user data FIFO. And then it reads the

‘USER_DATA’ register(user data FIFO output)

repeatedly as many as the number of

‘U_D_COUNT’ register. In this case, the host

had better use I2C burst read cycle for reading

speed efficiency.

If internal user data FIFO becomes full during user

data interrupts, ‘\UBUFF_FULL’ signal is

generated. And also the host reads user data by

using the same method as that of user data

interrupt.

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