GM0936TQ
Timing (TA=25¡ É, DVCC = AVCC = 3V)
PARAMETER
MIN
CLK Frequency
Sampling Rate
DOUT Delay from CLK
DIN Delay from CLK
TYP
2.048
8
MAX
35
35
UNIT
MHz
KHz
ns
ns
Clock timing requirements
Duty cycle, CLK
MIN NOM MAX
45% 50% 55%
UNIT
Transmit timing requirements
tsu(FSX)
th(FSX)
Setup time, FSX high before CLK ¡ é
Hold time, FSX high after CLK ¡ é
Receive timing requirements
tsu(FSR)
th(FSR)
tsu(DIN)
th(DIN)
Setup time, FSR high before CLK ¡ é
Hold time, FSR high after CLK ¡ é
Setup time, DIN high or low before CLK ¡ é
Hold time, DIN high or low after CLK ¡ é
MIN MAX
20 468
20 468
UNIT
ns
ns
MIN MAX
20 468
20 468
20
20
UNIT
ns
ns
ns
ns
11