P4C116-12DM Ver la hoja de datos (PDF) - Performance Semiconductor
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P4C116-12DM Datasheet PDF : 8 Pages
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P4C116
P4C116
ULTRA HIGH SPEED 2K x 8
STATIC CMOS RAMS
FEATURES
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
– 10/12/15/20/25/35 ns (Commercial)
– 15/20/25/35 ns (Military)
Low Power Operation
– 633/715 mW Active — 15, 20
– 550/633 mW Active — 25, 35
– 193/220 mW Standby (TTL Input)
Output Enable Control Function
Single 5V±10% Power Supply
Common Data I/O
Fully TTL Compatible Inputs and Outputs
Produced with PACE II TechnologyTM
Standard Pinout (JEDEC Approved)
– 24-Pin 300 mil DIP, SOIC, SOJ
– 24-Pin Rectangular LCC (300 x 400 mils)
– 28-Pin Square LCC (450 x 450 mils)
DESCRIPTION
The P4C116 is a 16,384-bit ultra high-speed static RAMs
organized as 2K x 8. The CMOS memories require no
clocks or refreshing and have equal access and cycle
times. Inputs are fully TTL-compatible. The RAMs oper-
ate from a single 5V±10% tolerance power supply. Cur-
rent drain is typically 10 µA from a 2.0V supply.
Access times as fast as 10 nanoseconds are available,
permitting greatly enhanced system operating speeds.
CMOS is used to reduce power consumption to a low 633
mW active, 193 mW standby.
The P4C116 is available in 24-pin 300 mil DIP, SOJ and
SOIC packages providing excellent board level densities.
The P4C116 is also available in 24-pin rectangular and
28-pin square LCC packages.
FUNCTIONAL BLOCK DIAGRAM
A
(6)
A
I/O 1
I/O 8
ROW
SELECT
INPUT
DATA
CONTROL
16,384-BIT
MEMORY
ARRAY
COLUMN I/O
COLUMN
SELECT
WE
CE
A
(5)
A
OE
PIN CONFIGURATIONS
A0 1
A1 2
A2 3
A3 4
A4 5
A5 6
A6 7
A7 8
I/O1 9
I/O2 10
I/O3 11
GND 12
24 VCC
23 A10
22 A9
21 WE
20 OE
19 A8
18 CE
17 I/O8
16 I/O7
15 I/O6
14 I/O5
13 I/O4
DIP (P4, D4), SOJ (J4), SOIC (S4)
DIP (P4 , DT4TO),OSPPOVVJIIE(EJ3WW), SOIC (S4 )
See Selection Guide Page for LCC
Means Quality, Service and Speed
1Q97
47
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