P4C116-25DM Ver la hoja de datos (PDF) - Performance Semiconductor

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P4C116-25DM

ULTRA HIGH SPEED 2K x 8 STATIC CMOS RAMS

Performance Semiconductor 

P4C116

AC TEST CONDITIONS

Input Pulse Levels

GND to 3.0V

Input Rise and Fall Times

3ns

Input Timing Reference Level

1.5V

Output Timing Reference Level

1.5V

Output Load

See Figures 1 and 2

TRUTH TABLE

Mode CE

Standby H

DOUT

Disabled L

Read

L

Write

L

OE WE

XX

HH

LH

XL

I/O

High Z

High Z

DOUT

High Z

Power

Standby

Active

Active

Active

DOUT

255Ω

+5

480Ω

30pF(5pF* for tHZ, tLZ, tOHZ,

tOLZ, tWZ and TOW)

DOUT

RTH = 166.5 Ω

VTH = 1.73 V

30pF(5pF* for tHZ, tLZ, tOHZ,

tOLZ, tWZ and tOW)

Figure 1. Output Load

* including scope and test fixture.

Figure 2. Thevenin Equivalent

Note:

Because of the ultra-high speed of the P4C116/L, care must be taken

when testing this device; an inadequate setup can cause a normal

functioning part to be rejected as faulty. Long high-inductance leads that

cause supply bounce must be avoided by bringing the VCC and ground

planes directly up to the contactor fingers. A 0.01 µF high frequency

capacitor is also required between VCC and ground. To avoid signal

reflections, proper termination must be used; for example, a 50Ω test

environment should be terminated into a 50Ω load with 1.73V (Thevenin

Voltage) at the comparator input, and a 116Ω resistor must be used in

series

with

D

OUT

to

match

166Ω

(Thevenin

Resistance).

52

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