CIRCC Ver la hoja de datos (PDF) - SMSC -> Microchip

Número de pieza

componentes Descripción

fabricante

CIRCC

Consumer Infrared Communications Controller

SMSC -> Microchip 

MASTER BLOCK CONTROL REGISTER

The Master Block Control Register contains the

CIrCC Power Down bit, two reset bits, the Master

Interrupt Enable bit, and the Register Block

Select lines (Table 14).

Address 7 is solely reserved for the Master Block

Control register. If the nSCE input is 0, the MBC

is always visible, regardless of the state of the

Register Block Select lines.

Address

A2 A1 A0

111

Table 14 - SCE Master Block Control Register

Direction

Description

D7

D6

D5

D4

D3

D2 D1 D0

R/W

Master Block Control Register

power master master

down reset int en.

error

reset

register block

select

Default

'00'hex

Register Block Select, bits 0-2

The Register Block Select bits enable access to

each of the eight possible register blocks. To

access a register block other than the default (0),

write a 3 bit register block number to the least

significant bits of the Master Block Control

Register. All subsequent reads and writes to

addresses 0 through 6 will access the registers in

the new block. To return to register block 0,

rewrite zeros to the register block select bits.

Error Reset, bit 4

Writing a one to the Error Reset bit will return all

of the SCE Line Status Register bits (Register

Block Zero) to their inactive states and reset the

Message Count bits, the Memory Count bits, and

the Message Byte Count registers to zero.

Master Interrupt Enable, bit 5

Setting the Master Interrupt Enable to one

enable the SCE interrupts onto the Interrupt

Request bus (IRQ) only if their individual

enables are active. Setting this bit to a zero

disables all SCE interrupts regardless of the

state of their individual enables.

Master Reset, bit 6

Setting the Master Reset bit to one forces data in

the SCE registers and SCE logical blocks into

the Power-On-Reset state. The Master Reset bit

is reset to zero following the reset operation.

Note: The Legacy bits (Register Block One,

Address Zero, Bits D0-D6) and the IR Half

Duplex Timeout are unaffected by Master Reset.

Power Down, bit 7

Setting this bit to a one causes only the SCE to

enter the low-power state. Power down mode

does not preclude access to the Master Block

Control register so that this mode can be

maintained entirely under software control. The

SCE can also be powered-down by the Power

Down input described in the Interface

Description.

24

Share Link: