CIRCC Ver la hoja de datos (PDF) - SMSC -> Microchip

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CIRCC

Consumer Infrared Communications Controller

SMSC -> Microchip 

REGISTER BLOCK ZERO

Register Block Zero contains the SCE Data

Register, the Interrupt Control/Status registers,

the Line Control/Status registers, and the Bus

Status register (Table 15). Typically, the controls

in Register Block Zero are used during

Consumer IR message transactions. Bits and

registers marked “reserved” in the table below

cannot be written and return 0s when read.

Programmers must set reserved bits to 0 when

writing to registers that contain reserved bits.

Address

A2 A1 A0

000

001

010

011

011

100

101

110

Direction

R/W

RO

R/W

RO

WO

R/W

R/W

RO

Table 15 - Register Block Zero

Description

D7

D6

D5

D4

D3

D2

D1

D0

Data Register

Interrupt Identification Register

active

frame

eom

raw fifo

IR

mode

busy

Interrupt Enable Register

reserved

active

frame

eom

raw fifo

IR

mode

busy

Line Status Register (read)

reserved

under-

run

over- frame

reserved

frame

run error

abort

Line Status Address Register (write)

reserved

reserved

Line Control Register A

status register

address

fifo

reset

reserved

raw tx raw rx

Line Control Register B

reserved

sce modes

bits

reserved

message count

Bus Status Register

not

fifo

empty full

time-

out

reserved

valid

frame

Default

‘00’hex

'00'hex

'00'hex

'00'hex

'00'hex

'00'hex

Data Register (Address 0)

Interrupt Identification Register (Address 1)

The Data Register is the FIFO access port.

Typically, the user will only write to the FIFO

when transmitting and read from the FIFO when

receiving. The host always has read access to

the FIFO regardless of the state of the SCE

Modes bits or the Loopback bit. Host read

access to the FIFO is blocked when the FIFO is

empty. The host has write access to the FIFO

only when the Loopback bit is inactive and the

SCE Modes bits are zero or Transmit mode is

enabled. Host write access to the FIFO is

blocked when the FIFO is full.

When an interrupt is active the associated

interrupt identifier bit in the IID register is also

active regardless of the state of its individual

interrupt enable or the Master Interrupt Enable,

except for the FIFO Interrupt. The Master

Interrupt Enable and the individual Interrupt

Enables serve only to enable the IID register

interrupts onto the Interrupt Request bus IRQ

shown in the Interface Description.

25

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