RTL8196E
Datasheet
7.2. DDR DRAM Controller
7.2.1. Features
• Interface (Bus Width): 16-bit
• Targeted DDR Frequency: Up to 193.75MHz
• Supports one Chip Select (MCS0#)
• Supports both DDR1 and DDR2
• Supported DDR DRAM Chip Specification
Bank Counts: 8
Row Counts: 4K (A0~A11), 8K (A0~A12), 16K (A0~A13)
Column Counts: 512 (A0~A8), 1K (A0~A9), 2K (A0~A9, A11), 4K (A0~A9, A11, A12)
• Programmable Timing Parameters: tRAS, tRP, tRCD, tCL, tREFI…
7.3. SPI Flash Controller
The SPI flash controller is a new design and incorporates new features.
7.3.1. Features
• Targeted SPI flash frequency: Up to 96.875MHz (when DRAM clock is 193.75MHz)
• Supports one chip
• In addition to a programmed I/O interface, also supports a memory-mapped I/O interface for read
operation
• Supports Read and Fast Read in memory-mapped I/O mode
7.3.2. Pin Mode and Definition of Serial and Dual I/O
Modes supported on the SPI flash interface:
Serial I/O Mode
• SDI: Flash chip data input pin
• SDO: Flash chip data output pin
Dual I/O Mode
• SDIO0 (SDI): Flash chip data bi-directional pin
• SDIO1 (SDO): Flash chip data bi-directional pin
5-Port 10/100M Ethernet Router Network Processor
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Track ID: JATR-3375-16 Rev. 1.0