CDB5343_06 Ver la hoja de datos (PDF) - Cirrus Logic
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CDB5343_06 Datasheet PDF : 21 Pages
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4.1.2
CS5343/4
Master Mode Operation
As clock Master, the CS5343/4 generates LRCK and SCLK synchronously on-chip. Table 3 shows the
available sample rates and associated clock ratios in Master Mode.
Speed Mode
Single-Speed Mode
Double-Speed Mode
MCLK/LRCK
Ratio
256x
512x
384x
768x
128x
256x
192x
384x
SCLK/LRCK
Ratio
64
64
64
64
64
64
64
64
Input Sample Rate Range (kHz)
4 - 54
4 - 54
4 - 54
4 - 54
86 - 108
86 - 108
86 - 108
86 - 108
Table 3. Speed Modes and the Associated Sample Rates (Fs) in Master Mode
4.1.2.1 Master Mode Speed Selection
During power-up in Master Mode, the LRCK and SCLK pins are inputs to configure speed mode and the
output clock ratio. The LRCK pin is pulled low internally to select Single-Speed Mode by default, but Dou-
ble-Speed Mode is accessed with a 10 kΩ pull-up resistor from LRCK to VA as shown in Table 4. Simi-
larly, the SCLK pin is internally pulled-low by default to select a 256x MCLK/LRCK ratio, but a
MCLK/LRCK ratio of 348x is accessed with a 10 kΩ pull-up resistor from SCLK to VA as shown in Table 4.
Following the power-up routine, the LRCK and SCLK pins become clock outputs.
Pin
LRCK
SCLK
Resistor Option
Internal Pull-Down to GND (100 kΩ)
External Pull-Up to VA (10 kΩ)
Internal Pull-Down to GND (100 kΩ)
External Pull-Up to VA (10 kΩ)
Clock Configuration
Single-Speed Mode (default)
Double-Speed Mode
256x MCLK/LRCK (default)
384x MCLK/LRCK
Table 4. Speed Mode Selection in Master Mode
4.1.3
Master Clock
The CS5343/4 requires a Master clock (MCLK) which runs the internal sampling circuits and digital filters.
There is also an internal MCLK divider which is automatically activated based on the frequency of the
MCLK. Table 4 lists some common audio output sample rates and the required MCLK frequency.
Master and Slave Mode
Sample Rate (kHz)
32
44.1
48
Speed Mode
SSM
SSM
SSM
MCLK(MHz)
256x
512x
8.912
16.384
11.289
22.579
12.288
24.576
MCLK (MHz)
384x
768x
12.288
24.576
16.934
33.868
18.432
36.864
Sample Rate (kHz)
88.2
96
Speed Mode
DSM
DSM
MCLK(MHz)
128x
256x
11.289
22.579
12.288
24.576
MCLK (MHz)
192x
384x
16.934
33.868
18.432
36.864
Table 5. Common MCLK Frequencies in Master and Slave Modes
14
DS687A4
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