L4925 Ver la hoja de datos (PDF) - STMicroelectronics

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L4925

Very low drop voltage regulator

STMicroelectronics 

L4925

Figure 4. Output voltage vs input voltage

Functional description

Figure 5. Quiescent current vs supply voltage

3.2

Reset circuit

The block circuit diagram of the reset circuit is shown in Figure 6. The reset circuit

supervises the output voltage. The reset threshold of 4.5 V is defined with the internal

reference voltage and standby output divider. The reset pulse delay time tRD, is defined with

the charge time of an external capacitor CT:

tRD

=

C-----T--------2---V---

2A

The reaction time of the reset circuit originates from the discharge time limitation of the reset

capacitor CT and it is proportional to the value of CT. The reaction time of the reset circuit

increases the noise immunity. Standby output voltage drops below the reset threshold only a

bit longer than the reaction time results in a shorter reset delay time.

The nominal reset delay time is generated for standby output voltage drops longer than

approximately 50 ms. The typical reset output waveforms are shown in Figure 7.

Doc ID 1770 Rev 8

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