NT35510 Ver la hoja de datos (PDF) - Novatek Microelectronics
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NT35510 Datasheet PDF : 211 Pages
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PRELIMINARY
NT35510
5.1.2.1 WRITE CYCLE SEQUENCE
The write cycle means that the host writes information (command or/and data) to the display via the interface.
Each write cycle (WRX high-low-high sequence) consists of 3 control (D/CX, RDX, WRX) and data signals
(D[23:0]). D/CX bit is a control signal, which tells if the data is a command or a data. The data signals are the
command if the control signal is low (=’0’) and vice versa it is data (=’1’).
WRX
D[23:0]
CSX
The host starts to control
D[23:0] lines when there is
a falling edge of the WRX
The display reads D[23:0]
lines when there is a
rising edge of the WRX
Fig. 5.1.1 80-Series WRX protocol
The host stops to
control D[23:0]
lines
1-byte command
2-byte command
n-byte command (number of parameter = n-1)
S CMD CMD PA1 CMD PA1
PAn-2 PAn-1 P
D/CX
RDX
WRX
D[23:0]
CMD CMD PA1 CMD PA1
PAn-2 PAn-1
Host D[23:0]
(MPU to Driver)
CMD CMD PA1 CMD PA1
PAn-2 PAn-1
Driver D[23:0]
(Driver to MPU)
Hi-Z
Hi-Z
CMD: Write command code
PA: Write parameter or RAM data
Hi-Z
Hi-Z
” ” Signals on D[23:0], D/CX, RDX and WRX pins
during CSX= H are ignored
Fig. 5.1.2 80-Series parallel bus protocol, write to register or display RAM
11/8/2010
25
Version 0.00
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