DM9102AF Ver la hoja de datos (PDF) - Davicom Semiconductor, Inc.
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DM9102AF Datasheet PDF : 71 Pages
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DM9102A
Single Chip Fast Ethernet NIC Controller
The DM9102A can assert this pin if it detects link status
change, or magic packet, or sample frame. The default is
“normal low, active high pulse”. The DM9102A also supports
High/Low and Pulse/Level options
97
X2
O Crystal feedback output pin used for crystal connection only
Leave this pin open if oscillator is used
98
X1/OSC
I Crystal or Oscillator Input (25MHZ50ppm)
25MHz Oscillator or series-resonance, fundamental
frequency crystal
102
BGRES
I Bandgap Voltage Reference Resistor
It connects to a 6.8K, 1% error tolerance resistor between
this pin and BGRESG pin to provide an accurate current
reference for DM9102A (10Base-T/100Base-TX Application)
101
BGRESG
I For Bandgap Circuit
It is used together with the BGRES pin
116
ISOLATE#
I Isolate
This isolate signal is used to isolate the DM9102A from the
system, and it is suitable for LAN on motherboard. When
isolate signal is active low, it disables the DM9102A function
and the DM9102A will not drive any outputs and sample inputs.
In this case, the power consumption is minimum
5.6 Power Pins
Pin No.
128QFP/128LQFP
100,107,108
103,104,111,112
8,9,15,22,28,29,35,37,45,
46,58,76,86,99,125
4,5,12,18,19,25,32,42,52,
53,61,70,82,96,120
Pin Name
AGND
AVDD
DGND
DVDD
I/O
Description
P Analog Ground
P Analog Power, +3.3V
P Digital Ground
P Digital Power, +3.3V
5.7 Note: LED Mode
Pin No.
128QFP/128LQFP
87
88
89
90
Non-external MII mode
MODE 0
MODE 1
External MII mode
MODE 0
MODE 1
LINK&ACT#
Link and traffic LED
FDX#
Full-duplex LED
SPEED100#
100Mbps Link LED
SPEED10#
10Mbps Link LED
ACT#
Traffic LED
FDX#
Full-duplex LED
SPEED100#
100Mbps Link LED
LINK#
Link LED
LINK&ACT#
Link and traffic LED
Non-LED
Non-LED
SPEED100#
100Mbps Link LED
ACT#
Traffic LED
Non-LED
Non-LED
SPEED100#
100Mbps Link LED
Final
11
Version: DM9102A-DS-F07
April 12, 2002
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