GL711FW Ver la hoja de datos (PDF) - Genesys Logic

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GL711FW

ATA/ATAPI to 1394 Native Bridge Two in One Solution

Genesys Logic 

GL711FW

Pin Description

PIN SYMBOL I/O DESCRIPTION

Power

31

RESET#

I Master reset signal, low active

2,10,29, VCC

- 3.3V power supply

41,54,62,

76,86

5,21,35, GND

- Ground

50,57,71,

84,90

Signals for Micro-Processor

92

OE#/RD# I/O When ENUP# = ‘1’: this active low signal enables the reading of

internal register.

When ENUP# = ‘0’: this bit is used for output enable flash memory

output

25

WR#

I UP: this active low signal enables the writing of internal register.

1,3,4, AD0-AD7 I/O When ENUP# = ‘1’: address & data bus bit 0 to bit 7 of external µP.

96-100

26

ALE

When ENUP# = ‘0’: data in-out of flash memory.

I ALE is used to enable the address latch that separates the

address from the data

95

CS#

I/O When ENUP# = ‘1’: This active low signal acts as the chip select

during register access cycle.

When ENUP# = ‘0’: This bit is an active low to select flash memory.

27

INT#

O This is an output pin to drive the active low interrupt signal to external

controller.

Signals for IDE interface

38-40 HDA0-2

O IDE device address. The 3-bit binary coded address asserted by the

ATA host to access a register or data port in the device.

37

HDCS0# O IDE chip select 0. The chip select signal from the ATA host used to

select the Command Block registers.

36

HDCS1# O IDE chip select 0. The chip select signal from the ATA host used to

select the Control Block registers.

46

HDIOW#(ST O Device I/O write (for PIO and Multi-word DMA mode)

OP)

Stop Ultra DMA burst (for UDMA mode)

Revision: 1.3

-12-

09/12/2001

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