GL640USB Ver la hoja de datos (PDF) - Genesys Logic

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GL640USB

IEEE-1284 to USB Bridge

Genesys Logic 

GL640USB, GL640USB-A

Data Memory Organization

The data memory is partitioned into two Banks which contain the General Purpose Registers,

MCU Function Registers and USB Function Registers. Bit RP0 is the bank select bit.

RP0 (STATUS<5>) = 1 → Bank 1

RP0 (STATUS<5>) = 0 → Bank 0

The lower locations of each Bank are reserved for MCU Function Registers. Above the MCU

Function Registers are the USB Registers, I/O Registers and General Purpose Registers

implemented as SRAM. Both Bank 0 and Bank 1 contain MCU Function Registers. USB

Registers are located in Bank 0, and I/O Resgiters are located in Bank 1. Some “high use” MCU

Function Registers from Bank 0 are mirrored in Bank 1 for code reduction and quicker access.

Data

Data

Memory

Memory

Address

Address

00h

INDR

80h

INDR

01h

TIMER

81h

PSCON

02h

PCL

82h

PCL

03h

STATUS

83h

STATUS

04h

INDAR

84h

INDAR

05h

85h

06h

PORT1

86h

PORT1CO

N

07h

PORT2

87h

PORT2CO

N

08h

88h

09h

89h

0Ah

PCHBUF

8Ah

PCHBUF

0Bh

INTEN

8Bh

INTEN

10~1Fh USB

90h~9Fh

I/O

Registers

Registers

20h

General

Revision 1.1

-10-

Jun. 7, 1999

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