GL811USB Ver la hoja de datos (PDF) - Genesys Logic

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GL811USB

USB 2.0 to ATA / ATAPI Bridge Controller

Genesys Logic 

GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller

3.2 Functional Overview

3.2.1 USB 2.0 TXCVR

The USB 2.0 Transceiver is the analog circuitry to handle the USB HS/FS

signaling.

3.2.2 UTMI (USB 2.0 Transceiver Macrocell Interface) Logic

The UTMI Logic is compliant to Intel’s UTMI specification 1.01. This block handles

the low level USB protocol and signaling. The major jobs of UTMI Logic is data and

clock recovery, NRZI encoding/decoding, Bit Stuffing/De-stuffing, USB2.0 test

modes supporting and serial / parallel conversion.

3.2.3 SIE (Serial Interface Engine)

The SIE contains the USB packet ID and address recognition logic, and other

sequencing and state machine logic to handle USB packets and transactions.

3.2.4 PLL

10XPLL provides the 120MHz clock output for UTMI Logic block. UTMI operates in

120MHz for USB HS data processing. 40XPLL block will provide 480MHz for USB

HS data transmission.

3.2.5 CLKGEN

CLKGEN is the clock generator block for the logic blocks. It generates 15MHz

clock for micro controller, 12MHz for PIO mode, 48MHz for MDMA mode, 96MHz

for UDMA mode, and 30MHz clock for UTMI, SIE, and FIFO.

3.2.6 CPU

The CPU is the control center of GL811USB. It’s an 8-bit micro controller operating

in 15MHz, 7.5 MIPS. After receiving a USB command, it decodes the host

command, then it re-assigns tasks to the IDE engine, GPIO, FIFO, and response

proper data/status to USB host.

3.2.7 IDE Engine

The IDE engine is extended from standard ATA / ATAPI protocol. It supports PIO

mode, multiword DMA mode, and ultra DMA mode data transfers.

©2000-2002 Genesys Logic Inc.—All rights reserved.

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