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EI68C681

DUAL UART

IMP, Inc

EI68C681 Datasheet PDF : 2 Pages

1 2

Semiconductor, Inc.

Ei68C681

Ei88C681

DUAL UART

FEATURES

•

Full duplex, dual channel asynchronous

receiver and transmitter

•

Quadruple-buffered receiver and transmitter

•

Stop bits programmable in 1/16-bit increments

•

Internal bit rate generator with 23 bit rates

•

Independent bit rate selection for each Rx

and Tx

•

Maximum bit rate: 1 x clock - 2 Mb/sec., 16

x clock- 250 Kb/sec.

•

Normal, auto-echo, local loop-back and

remote loop-back modes

•

Multi-function 16-bit counter/timer

•

Interrupt output with 8 maskable interrupt

ing conditions

•

Interrupt vector output on acknowledge

•

Programmable interrupt daisy chain

•

Up to 15 I/O pins (depending on package

and version)

•

Multidrop mode compatible with 8051 nine-

bit mode

•

On-chip oscillator for crystal

•

Stand-by mode to reduce operating power

•

Advanced CMOS low power technology

DESCRIPTION

The Epic Ei88C681/Ei68C681 DUART Dual Universal

Asynchronous Receiver and Transmitter is a data com-

munication device that provides two fully independent full

duplex asynchronous communication channels in a

single package. The DUART is designed for use in

microprocessor based systems and may be used in a

polled or interrupt driven environment.

Two basic versions of the DUART are available, each

optimized for use with various microprocessor families:

the 88C81 for 8085/85, 8080/88, Z80, Z8000, 68XX and

65XX family based systems., and the 68C681 for 68000

family based systems. A programmable mode of the

Ei88C681 versions provides an interrupt daisy chain for

use in Z80 and Z8000 based systems. The bus inter-

faces are however general enough to allow interfacing

with other microprocessors and microcontrollers. The

88C681 and 68C681 are enhanced versions of the

Signetics 2681 and the Motorola 68681, and are pin and

function compatible with those devices. Each channel of

the DUART may be independently programmed for

operating mode and data format. The operating speed of

each receiver and transmitter can beselected from baud

rate generator, from the multi-purpose on chip

counter/timer or from an external 1 x or 16 x clock.The bit

rate generator can operate directly from a crystal connect-

ed across two pins or from an external clock. The ability to

independently program the operating speed of the receiv-

er and transmitter of each channel makes the DUART

attractive for split-speed channel application such as clus-

tered terminal systems. Both receive and transmit data is

quadruple-buffered in on-chip FIFO to minimize the risk of

receiver overrun or to reduce overhead in interrupt-drive

applications.

PIN CONFIGURATION

Part Numbers May Be Marked With "IMP" or "Ei."

A1 1

40 VCC

IP3 2

39 IP4

A2 3

38 IP5

IP1 4

37 IACK•

A3 5

36 IP2

A4 6

IPO 7

35 CS•

E 34 RESET•

R/W• 8

33 X2

DTACK• 9

6 32 X1/CLK

RxDB 10

31 RxDA

TxDB 11 C 30 TxDA

OP1 12 6 29 OP0

OP3 13

28 OP2

OP5 14

27 OP4

OP7 15

26 OP6

D1 16

25 D0

D3 17

24 D2

D5 18

D7 19

GND 20

23 D4

22 D6

21 INTR•

40-PIN DIP

A0 1

40 VCC

IP3 2

39 IP4/IEI

A1 3

38 IP5/IEO

IP1 4

37 IP6/IACKN

A2 5

36 IP2

6 5 4 3 2 1 44 43 42 41 40

A3 6

IPO 7

WRN 8

RDN 9

35 CEN

34 RESET

33 X2

A4 7

IP0 8

R/WN 9

32 X1/CLK

DTACK • 10

39 CS •

38 RESET

37 X2

36 X1/CLK •

A3 7

IP0 8

WR• 9

RD• 10

RxDB 10 8 31 RxDA

RXDB 11

35 RXDA

RXDB 11

TxDB 11 C 30 TxDA

NC 12

Ei68C681

34 NC

NC 12

OP1 12 6 29 OP0

TXDB 13

33 TXDA

TXDB 13

OP3 13 8 28 OP2

OP5 14

27 OP4

OP7 15

26 OP6

D1 16

25 D0

OP1 14

OP3 15

OP5 16

OP7 17

32 OP0

31 OP2

30 OP4

29 OP6