FDC37B80X Ver la hoja de datos (PDF) - SMSC -> Microchip
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FDC37B80X
SMSC -> Microchip
FDC37B80X Datasheet PDF : 194 Pages
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FIGURE 14B - EPP 1.7 DATA OR ADDRESS WRITE CYCLE PARAMETERS
NAME
DESCRIPTION
t1 nIOW Asserted to PDATA Valid
t2 Command Deasserted to nWRITE Change
t3 nWRITE to Command
t4 nIOW Deasserted to Command Deasserted (Note 2)
t5 Command Deasserted to PDATA Invalid
t6 Time Out
t8 SDATA Valid to nIOW Asserted
t9 nIOW Deasserted to DATA Invalid
t10 nIOW Asserted to IOCHRDY Asserted
t11 nWAIT Deasserted to IOCHRDY Deasserted
t12 IOCHRDY Deasserted to nIOW Deasserted
t13 nIOW Asserted to nWRITE Asserted
t16 PDATA Valid to Command Asserted
t17 Ax Valid to nIOW Asserted
t18 nIOW Deasserted to Ax Invalid
t19 nIOW Deasserted to nIOW or nIOR Asserted
t20 nWAIT Asserted to IOCHRDY Deasserted
t21 Command Deasserted to nWAIT Deasserted
MIN TYP MAX UNITS
0
50
ns
0
40
ns
5
35
ns
50
ns
50
ns
10
12
µs
10
ns
0
ns
0
24
ns
40
ns
10
ns
0
50
ns
10
35
ns
40
ns
10
µs
100
ns
45
ns
0
ns
Note 1: nWRITE is controlled by clearing the PDIR bit to "0" in the control register before performing
an EPP Write.
Note 2: The number is only valid if nWAIT is active when IOW goes active.
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