LPC47N227TQFP Ver la hoja de datos (PDF) - SMSC -> Microchip

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LPC47N227TQFP

100 Pin Super I/O with LPC Interface for Notebook Applications

SMSC -> Microchip 

BIT 1 WRITE PROTECT

Active high status of the WRITE PROTECT disk interface input. A logic "1" indicates that the disk is write

protected.

BIT 2 INDEX

Active high status of the INDEX disk interface input.

BIT 3 nHEAD SELECT

Active low status of the HDSEL disk interface input. A logic "0" selects side 1 and a logic "1" selects side 0.

BIT 4 TRACK 0

Active high status of the TRK0 disk interface input.

BIT 5 STEP

Active high status of the latched STEP disk interface output pin. This bit is latched with the STEP output

going active, and is cleared with a read from the DIR register, or with a hardware or software reset.

BIT 6 DMA REQUEST

Active high status of the DMA request pending.

BIT 7 INTERRUPT PENDING

Active high bit indicating the state of the Floppy Disk Interrupt.

Status Register B (SRB)

Address 3F1 READ ONLY

This register is read-only and monitors the state of several disk interface pins in PS/2 and model 30 modes.

The SRB can be accessed at any time when in PS/2 mode. In the PC/AT mode the data bus pins D0 - D7

are held in a high impedance state for a read of address 3F1.

PS/2 Mode

7

1

RESET 1

COND.

6

5

4

3

2

1

0

1 DRIVE WDATA RDATA WGATE MOT MOT

SEL0 TOGGLE TOGGLE

EN1 EN0

1

0

0

0

0

0

0

BIT 0 MOTOR ENABLE 0

Active high status of the MTR0 disk interface output pin. This bit is low after a hardware reset and

unaffected by a software reset.

BIT 1 MOTOR ENABLE 1

Active high status of the MTR1 disk interface output pin. This bit is low after a hardware reset and

unaffected by a software reset.

BIT 2 WRITE GATE

Active high status of the WGATE disk interface output.

BIT 3 READ DATA TOGGLE

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