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FDC87W21

Power I/O Controller with Fast Infrared Support

SMSC -> Microchip 

At the start of a command the FIFO is always

disabled and command parameters must be

sent based upon the RQM and DIO bit settings

in the main status register. When the FDC

enters the command execution phase, it clears

the FIFO of any data to ensure that invalid data

are not transferred.

An overrun and underrun will terminate the

current command and the data transfer. Disk

writes will complete the current sector by

generating a 00 pattern and valid CRC. Reads

require the host to remove the remaining data

so that the result phase may be entered.

DMA transfers are enabled with the SPECIFY

command and are initiated by the FDC by

activating the DRQ pin during a data transfer

command. The FIFO is enabled directly by

asserting nDACK and addresses need not be

valid.

Note that if the DMA controller is programmed

to function in verify mode a pseudo read is

performed by the FDC based only on nDACK.

This mode is only available when the FDC has

been configured into byte mode (FIFO disabled)

and is programmed to do a read. With the FIFO

enabled the above operation is performed by

using the new VERIFY command. No DMA

operation is needed.

Data Separator

The function of the data separator is to lock onto

the incoming serial read data. When a lock is

achieved the serial front end logic of the chip is

provided with a clock which is synchronized to

the read data. The synchronized clock, called

the Data Window, is used to internally sample

the serial data portion of the bit cell, and the

alternate state samples the clock portion. Serial

to parallel conversion logic separates the read

data into clock and data bytes.

The Digital Data Separator (DDS) has three

parts: control logic, error adjustment, and speed

tracking. The DDS circuit cycles once every 12

clock cycles ideally. Any data pulse input will be

synchronized and then adjusted by immediate

error adjustment. The control logic will generate

RDD and RWD for every pulse input. During any

cycle where no data pulse is present, the DDS

cycles are based on speed. A digital integrator is

used to keep track of the speed changes in the

input data stream.

Write Precompensation

The write precompensation logic is used to

minimize bit shifts in the RDDATA stream from

the disk drive. Shifting of bits is a known

phenomenon in magnetic media and is

dependent on the disk media and the floppy

drive.

The FDC monitors the bit stream that is being

sent to the drive. The data patterns that require

precompensation are well known. Depending

upon the pattern, the bit is shifted either early or

late relative to the surrounding bits.

Perpendicular Recording Mode

The FDC is also capable of interfacing directly

to perpendicular recording floppy drives.

Perpendicular recording differs from the

traditional longitudinal method in that the

magnetic bits are oriented vertically. This

scheme packs more data bits into the same

area.

FDCs with perpendicular recording drives can

read standard 3.5" floppy disks and can read

and write perpendicular media. Some

manufacturers offer drives that can read and

write standard and perpendicular media in a

perpendicular media drive.

A single command puts the FDC into

perpendicular mode. All other commands

operate as they normally do. The perpendicular

mode requires a 1 Mbps data rate for the FDC.

At this data rate the FIFO eases the host

interface bottleneck due to the speed of data

transfer to or from the disk.

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