LPC61W492 Ver la hoja de datos (PDF) - SMSC -> Microchip

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LPC61W492

Integrated Super I/O Controller for LPC Bus with Game and MIDI Ports/Plus Hardware Monitoring Functions

SMSC -> Microchip 

PIN DESCRIPTION

Note: Please refer to Section 13.2 DC CHARACTERISTICS for details.

I/O8t

I/O12t

I/O12tp3

I/OD12t

I/O24t

OUT12t

OUT12tp3

OD12

OD24

INcs

INt

INtd

INts

INtsp3

TTL level bi-directional pin with 8 mA source-sink capability

TTL level bi-directional pin with 12 mA source-sink capability

3.3V TTL level bi-directional pin with 12 mA source-sink capability

TTL level bi-directional pin open drain output with 12 mA sink capability

TTL level bi-directional pin with 24 mA source-sink capability

TTL level output pin with 12 mA source-sink capability

3.3V TTL level output pin with 12 mA source-sink capability

Open-drain output pin with 12 mA sink capability

Open-drain output pin with 24 mA sink capability

CMOS level Schmitt-trigger input pin

TTL level input pin

TTL level input pin with internal pull down resistor

TTL level Schmitt-trigger input pin

3.3V TTL level Schmitt-trigger input pin

LPC Interface

SYMBOL

CLKIN

nPME

PCICLK

nLDRQ

SERIRQ

LAD[3:0]

nLFRAME

nLRESET

SUSCLKIN

PIN

18

19

21

22

23

24-27

29

30

75

I/O

INt

OD12

INtp3

O12tp3

I/OD2tp3

I/O12tp3

INtsp3

INtsp3

INts

FUNCTION

System clock input. According to the input frequency

24MHz or 48MHz, it is selectable through register. Default

is 24MHz input.

Generated PME event.

PCI clock input.

Encoded DMA Request signal.

Serial IRQ Input/Output.

These signal lines communicate address, control, and data

information over the LPC bus between a host and a

peripheral.

Indicates start of a new cycle or termination of a broken

cycle.

Reset signal. It can be connected to nPCIRST signal on

the host.

32kHz clock input, for CIR only.

9

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