LPC47U322 Ver la hoja de datos (PDF) - SMSC -> Microchip

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LPC47U322

128 Pin Enhanced Super I/O Controller for LPC Bus with Consumer Features and SMBus Controller

SMSC -> Microchip 

QFP

PIN #

94

95

NAME

BUSY/nMTR1

nACK/nDS1

96 nERROR/nHDSEL

97 nALF/nDRVDEN0

98 nSTROBE/nDS0

112 RXD

113 TXD

114 nDSR

115 nRTS

116 nCTS

117 nDTR

118 nRI

119 nDCD

19, VCC

80,

121

15 VTR

6, 32,

57,

87,

99

52

1

VSS

AVSS

VREF

16 CLKI32

20 CLOCKI

FUNCTION

BUFFER

TYPE

Busy/FDC Motor On

Acknowledge/FDC Drive

Select 1

Error/FDC Head Select

I/OD12

I/OD12

I/OD12

Autofeed Output/FDC

Density Select

Strobe Output/FDC Drive

Select

(OD14/

OP14)/OD14

(OD14/

OP14)/OD14

SERIAL PORT INTERFACE

Receive Data

IS

Transmit Data

O12

Data Set Ready

I

Request to Send

O8

Clear to Send

I

Data Terminal Ready

O6

Ring Indicator

I

Data Carrier Detect

I

POWER PINS

+3.3 Volt Supply Voltage

Standby Supply Voltage

(Note 5)

Ground

Analog Ground

Reference Voltage (5V or

3.3V)

CLOCK PINS

32.768kHz Standby Clock

IS

Input (Note 3)

14.318MHz Clock Input

IS

BUFFER MODE PER

FUNCTION (NOTE 1)

I/OD12

I/OD12

I/OD12

(OD14/OP14)/ OD14

(OD14/OP14)/ OD14

IS

O12

I

O8

I

O6

I

I

IS

IS

Note: There are no internal pullups on any of the pins in the LPC47U32x.

Note: The "n" as the first letter of a signal name indicates an "Active Low" signal.

Note 1: Buffer Modes per function on multiplexed pins are separated by a slash “/”. Buffer Modes in

parenthesis represent multiple buffer modes for a single pin function.

Note 2: The nLPCPD pin may be tied high. The LPC interface will function properly if the

nPCI_RESET signal follows the protocol defined for the nLRESET signal in the “Low Pin

Count Interface Specification”.

Note 3: If the 32kHz input clock is not used the CLKI32 pin must be grounded. There is a bit in the

configuration register at 0xF0 in Logical Device A that indicates whether or not the 32kHz

10

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