LPC47U327 Ver la hoja de datos (PDF) - SMSC -> Microchip

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LPC47U327

128 Pin Enhanced Super I/O Controller for LPC Bus with Consumer Features and SMBus Controller

SMSC -> Microchip 

LPC Interface

The following sub-sections specify the

implementation of the LPC bus.

LPC Interface Signal Definition

The signals required for the LPC bus interface

are described in the table below. LPC bus

signals use PCI 33MHz electrical signal

characteristics.

SIGNAL NAME

LAD[3:0]

nLFRAME

nPCI_RESET

nLDRQ

nIO_PME

nLPCPD

SER_IRQ

PCI_CLK

TYPE

I/O

Input

Input

Output

OD

Input

I/O

Input

Table 3 – LPC Interface Signal Definition

DESCRIPTION

LPC address/data bus. Multiplexed command, address and data

bus.

Frame signal. Indicates start of new cycle and termination of broken

cycle

PCI Reset. Used as LPC Interface Reset.

Encoded DMA/Bus Master request for the LPC interface.

Power Mgt Event signal. Allows the LPC47U32x to request wakeup.

Powerdown Signal. Indicates that the LPC47U32x should prepare

for power to be shut on the LPC interface.

Serial IRQ.

PCI Clock.

LPC Cycles

The following cycle types are supported by the LPC protocol.

Table 4 – LPC Cycle Transfer Size

CYCLE TYPE

TRANSFER SIZE

I/O Write

1 Byte Transfer

I/O Read

1 Byte Transfer

DMA Write

1 byte

DMA Read

1 byte

The LPC47U32x ignores cycles that it does do not support.

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