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LPC47U32X

128 Pin Enhanced Super I/O Controller for LPC Bus with Consumer Features and SMBus Controller

SMSC -> Microchip 

Field Definitions

The data transfers are based on specific fields

that are used in various combinations,

depending on the cycle type. These fields are

driven onto the LAD[3:0] signal lines to

communicate address, control and data

information over the LPC bus between the host

and the LPC47U32x. See the Low Pin Count

(LPC) Interface Specification Revision 1.0 from

Intel, Section 4.2 for definition of these fields.

Data transfers are assumed to be exactly 1-

byte. If the CPU requested a 16 or 32-bit

transfer, the chipset will break it up into 8-bit

transfers.

See the Low Pin Count (LPC) Interface

Specification Reference, for the sequence of

cycles for the I/O Read and Write cycles.

DMA Read and Write Cycles

nLFRAME Usage

nLFRAME is used by the host to indicate the

start of cycles and the termination of cycles due

to an abort or time-out condition. This signal is

to be used by the LPC47U32x to know when to

monitor the bus for a cycle.

This signal is used as a general notification that

the LAD[3:0] lines contain information relative to

the start or stop of a cycle, and that the

LPC47U32x monitors the bus to determine

whether the cycle is intended for it. The use of

nLFRAME allows the LPC47U32x to enter a

lower power state internally. There is no need

for the LPC47U32x to monitor the bus when it is

inactive, so it can decouple its state machines

from the bus, and internally gate its clocks.

DMA read cycles involve the transfer of data

from the host (main memory) to the

LPC47U32x. DMA write cycles involve the

transfer of data from the LPC47U32x to the host

(main memory). Data will be coming from or

going to a FIFO and will have minimal Sync

times. Data transfers to/from the LPC47U32x

are 1, 2 or 4 bytes.

See the Low Pin Count (LPC) Interface

Specification Reference, for the field definitions

and the sequence of the DMA Read and Write

cycles.

DMA Protocol

DMA on the LPC bus is handled through the use

of the nLDRQ lines from the LPC47U32x and

special encodings on LAD[3:0] from the host.

When the LPC47U32x samples nLFRAME

active, it immediately stops driving the LAD[3:0]

signal lines on the next clock and monitor the

bus for new cycle information.

The nLFRAME signal functions as described in

the Low Pin Count (LPC) Interface Specification

Reference.

I/O Read and Write Cycles

The LPC47U32x is the target for I/O cycles. I/O

cycles are initiated by the chipset for register or

FIFO accesses, and will generally have minimal

Sync times. The minimum number of wait-

states between bytes is 1. EPP cycles will

depend on the speed of the external device, and

may have much longer Sync times.

The DMA mechanism for the LPC bus is

described in the Low Pin Count (LPC) Interface

Specification Reference.

Power Management

CLOCKRUN Protocol

The nCLKRUN pin is not implemented in the

LPC47U32x. See the Low Pin Count (LPC)

Interface Specification Reference section, 8.1.

LPCPD Protocol

See the Low Pin Count (LPC) Interface

Specification Reference, section 8.2.

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