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LPC47U322

128 Pin Enhanced Super I/O Controller for LPC Bus with Consumer Features and SMBus Controller

SMSC -> Microchip 

SYNC Protocol

See the Low Pin Count (LPC) Interface

Specification Reference, section 4.2.1.8 for a

table of valid SYNC values.

Typical Usage

The SYNC pattern is used to add wait states.

For read cycles, the LPC47U32x immediately

drives the SYNC pattern upon recognizing the

cycle. The chipset immediately drives the sync

pattern for write cycles. If the LPC47U32x needs

to assert wait states, it does so by driving 0101

or 0110 on LAD[3:0] until it is ready, at which

point it will drive 0000 or 1001. The LPC47U32x

will choose to assert 0101 or 0110, but not

switch between the two patterns.

The data (or wait state SYNC) will immediately

follow the 0000 or 1001 value.

The SYNC value of 0101 is intended to be used

for normal wait states, wherein the cycle will

complete within a few clocks. The LPC47U32x

uses a SYNC of 0101 for all wait states in a

DMA transfer.

The SYNC value of 0110 is intended to be used

where the number of wait states is large. This is

provided for EPP cycles, where the number of

wait states could be quite large (>1

microsecond). However, the LPC47U32x uses a

SYNC of 0110 for all wait states in an I/O

transfer.

The SYNC value is driven within 3 clocks.

SYNC Timeout

The SYNC value is driven within 3 clocks. If the

chipset observes 3 consecutive clocks without a

valid SYNC pattern, it will abort the cycle.

The LPC47U32x does not assume any particular

timeout. When the chipset is driving SYNC, it

may have to insert a very large number of wait

states, depending on PCI latencies and retries.

SYNC Patterns and Maximum Number of

SYNCS

If the SYNC pattern is 0101, then the chipset

assumes that the maximum number of SYNCs

is 8.

If the SYNC pattern is 0110, then no maximum

number of SYNCs is assumed. The

LPC47U32x has protection mechanisms to

complete the cycle. This is used for EPP data

transfers and should utilize the same timeout

protection that is in EPP.

SYNC Error Indication

The LPC47U32x reports errors via the LAD[3:0]

= 1010 SYNC encoding.

If the host was reading data from the

LPC47U32x, data will still be transferred in the

next two nibbles. This data may be invalid, but

it will be transferred by the LPC47U32x. If the

host was writing data to the LPC47U32x, the

data had already been transferred.

In the case of multiple byte cycles, such as DMA

cycles, an error SYNC terminates the cycle.

Therefore, if the host is transferring 4 bytes from

a device, if the device returns the error SYNC in

the first byte, the other three bytes will not be

transferred.

I/O and DMA START Fields

I/O and DMA cycles use a START field of 0000.

Reset Policy

The following rules govern the reset policy:

1. When nPCI_RESET goes inactive (high),

the clock is assumed to have been running

for 100usec prior to the removal of the reset

signal, so that everything is stable. This is

the same reset active time after clock is

stable that is used for the PCI bus.

2. When nPCI_RESET goes active (low):

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