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SMC91C95 Ver la hoja de datos (PDF) - SMSC -> Microchip

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componentes Descripción
Lista de partido
SMC91C95 Datasheet PDF : 139 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
PIN NO.
113
NAME
35, 36,
38-43,
45-50,
52, 53
54
Address 0-
15
Address 16
nFlash
Memory
Write
55
Address 17
nFlash
Memory
Chip Select
56
Address 18
57
Address 19
Card Enable
1
34
Address
Enable
DESCRIPTION OF PIN FUNCTIONS
SYMBOL
TYPE
DESCRIPTION
nROM/
nPCMCIA
I/O4 with
pullup
This pin is sampled at the end of RESET.
When this pin is sampled low the SMC91C95
is configured for PCMCIA operation and all
pin definitions correspond to the PCMCIA
mode. For ISA operation this pin is left open
and is used as a ROM chip select output that
goes active when nMEMR is low and the
address bus contains a valid ROM address.
A0-A15
I
Input address lines 0 through 15.
A16
nFWE
A17
nFCS
A18
A19
nCE1
AEN
nREG
I
ISA - Input address line 16.
O4
PCMCIA - Output. Flash Memory Write
Enable used for programming the attribute
memory. Goes active (low) when nWE=0 and
WRATTRIB=1 (in ECOR bit 3).
I
ISA - Input address line 17.
O4
PCMCIA - Output. Flash Memory Chip Select
used to access attribute memory. Goes active
(low) when nREG=0, nCE1=0 and A15=0.
I
Input address line 18.
I with pullup ISA - Input address line 19.
PCMCIA - Card Enable 1 input. Used to
select card on even byte accesses.
I with pullup
ISA - Address enable input. Used as an
address qualifier. Address decoding is only
enabled when AEN is low.
PCMCIA - Attribute memory and IO select
input. Asserted when the card attribute space
or IO space is being accessed.
9

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