FDC37N958FRTQFP Ver la hoja de datos (PDF) - SMSC -> Microchip

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FDC37N958FRTQFP

Notebook I/O Controller with Enhanced Keyboard and System Control

SMSC -> Microchip 

System Interface Pins

Table 5 gives the state of the system interface

pins in the powerdown state. Pins unaffected by

the powerdown are labeled "Unchanged". Input

pins are "Disabled" to prevent them from causing

currents internal to the FDC37N958FR when they

have indeterminate input values.

Table 4 - PC/AT and PS/2 Available Registers

BASE + ADDRESS AVAILABLE REGISTERS

PC/AT PS/2 (Model 30)

ACCESS

PERMITTED

Access to these registers DOES NOT wake up the FDC37N958FR

00H

----

SRA

R

01H

----

SRB

R

02H

DOR (1)

DOR (1)

R/W

03H

---

---

---

04H

DSR (1)

DSR (1)

W

06H

---

---

---

07H

DIR

DIR

R

07H

CCR

CCR

W

Access to these registers wakes up the FDC37N958FR

04H

MSR

MSR

R

05H

Data

Data

R/W

Note 1: Writing to the DOR or DSR does not wake up the FDC37N958FR, however, writing any of the

motor enable bits or doing a software reset (via DOR or DSR reset bits) will wake up the

FDC37N958FR.

SMSC DS – FDC37N958FR

Page 19

Rev. 09/01/99

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