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COM20022

10Mbps ARCNET controller with 2Kx8 on-board RAM

SMSC -> Microchip 

DREQ

nWR

DMAEN bit

minimum 4TARB

Writing Address

Pointer Low

TARB is the ARBITRATION Clock Period. It depends on the TOPR and

SLOW-ARB bit. TOPR is the period of operation clock frequency (output

of the clock multiplier). It depends on the CKUP1 and CKUP0 bits.

TARB = TOPR @ SLOW-ARB = 0

TARB = 2 TOPR @ SLOW-ARB = 1

FIGURE 4 - DREQ PIN FIRST ASSERTION TIMING FOR ALL DMA MODES

As an example of gating by cycle, in an ISA bus

system, the Refresh period is 15#S. Continuous

transfer by DMA must be less than 15#S to

prevent blocking by the Refresh cycle. A DMA

cycle of consecutive DMA cycles is

approximately 1uS. The DMA overhead time is

approximately 2.5#S. The Refresh execution

time is 500nS. This computes to 15#S - 2.5#S -

500nS = 12#S or 12 cycles. Therefore the

DREQ pin must be negated every 12 cycles.

Figure 5 illustrates the rough timing of the

Programmable-Burst mode DMA transfer.

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