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COM20022V-HT

10Mbps ARCNET controller with 2Kx8 on-board RAM

SMSC -> Microchip 

The following sequences show the data transfer

for a DMA read and a DMA write. The transfer of

data between system memory and internal RAM

functions as a memory to I/O DMA transfer.

Since it is treated as an I/O device, the

COM20022 has to create the RAM address.

Therefore the COM20022’s address pointers

must be programmed before starting the DMA

transfers.

DMA Data Transfer Sequence (I/O to Memory:

Read A Packet)

step1: Set DMA-controller (ex. 8237)

step2: Set DRQPOL, TCPOL, DMAMD1 and

DMAMD0 bits

>>Finished DMA SETUP

>>A packet received

step3: Set address, byte count and etc. of

DMA controller

step4: Set pointer High and Low

(RDDATA=1,AUTOINC=1,

DMAEN=0)

step5: Read SID, DID, CP in the received

packet

step6: Set DMAEN=1 (RDDATA=1,

AUTOINC=1)

step7: DMAEND=1 in Mask REG.

step8: Set pointer = CP

>>DREQ is asserted by step8

>>Interrupt occurs upon finishing

DMA

DMA Data Transfer Sequence (Memory to I/O:

Write A Packet)

step1: Set DMA-controller (ex. 8237)

step2: Set DRQPOL, TCPOL, DMAMD1 and

DMAMD0 bits

>>Finished DMA SETUP

step3: Set address, byte count and etc. of

DMA controller

step4: Set pointer High and Low

(RDDATA=0,AUTOINC=1, DMAEN = 0)

step5: Write SID,DID,CP in the sending

packet

step6: Set DMAEN=1 (RDDATA=0,

AUTOINC=1)

step7: DMAEND=1 in Mask REG.

step8: Set pointer = CP

>>DREQ is asserted by step8

>>Interrupt occurs upon finishing

DMA transfer

step9: Write Enable Transmit command to

command register

High Speed CPU Bus Timing Support

High speed CPU bus support was added to the

COM20022. The reasoning behind this is as

follows: With the Host interface in Non-

multiplexed Bus mode, I/O address and Chip

Select signals must be stable before the read

signal is active and remain after the read signal

is inactive. But the High Speed CPU bus timing

doesn't adhere to these timings. For example, a

RISC type single chip microcontroller (like the

HITACHI SH-1 series) changes I/O address at

the same time as the read signal. Therefore,

several external logic ICs would be required to

connect to this microcontroller.

In addition, the Diagnostic Status (DIAG) register

is cleared automatically by reading itself. The

internal DIAG register read signal is generated

by decoding the Address (A2-A0), Chip Select

(nCS) and Read (nRD) signals. The decoder will

generate a noise spike at the above tight timing.

The DIAG register is cleared by the spike signal

without reading itself. This is unexpected

operation. Reading the internal RAM and Next

Id Register have the same mechanism as

reading the DIAG register.

Therefore, the address decode and host

interface mode blocks were modified to fit the

above CPU interface to support high speed CPU

bus timing. In Intel CPU mode (nRD, nWR

mode), 3 bit I/O address (A2-A0) and Chip

Select (nCS) are sampled internally by Flip-

Flops on the falling edge of the internal delayed

nRD signal. The internal real read signal is the

more delayed nRD signal. But the rising edge of

nRD doesn't delay. By this modification, the

internal real address and Chip Select are stable

while the internal real read signal is active.

Refer to figure 8 on the following page.

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