COM20022 Ver la hoja de datos (PDF) - SMSC -> Microchip
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Lista de partido
COM20022 Datasheet PDF : 88 Pages
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PIN NO
44,45,
46
1,2,4,
7,9,
10,12,
13
47, 48,
3,5,
14-17
37
39
31
34
36
42
26
33
NAME
Address
0-2
Data 0-7
Data 8-15
nWrite/
Direction
nRead/
nData
Strobe
nReset In
nInterrupt
nChip
Select
nI/O
16 Bit
Indicator
Read/Write
Bus Timing
Select
DMA
Request
DESCRIPTION OF PIN FUNCTIONS
SYMBOL I/O
DESCRIPTION
MICROCONTROLLER INTERFACE
A0/nMUX
IN On a non-multiplexed mode, A0-A2 are address
A1
IN input bits. (A0 is the LSB) On a multiplexed
address/data bus, nMUX tied Low, A1 is left open,
and ALE is tied to the Address Latch Enable signal.
A2/ALE
IN A1 is connected to an internal pull-up resistor.
AD0-AD2, I/O On a non-multiplexed bus, these signals are used as
D3-D7
the lower byte data bus lines. On a multiplexed
address/data bus, AD0-AD2 act as the address lines
(latched by ALE) and as the low data lines. D3-D7
are always used for data only. These signals are
connected to internal pull-up resistors.
D8-D15
I/O D8-D15 are always used as the higher byte data bus
lines only for 16bit internal RAM access. When the
16bit access is disabled, these signals are always
Hi-Z. Enabling or disabling the 16bit access is
programmable. A data swapper is built in. These
signals are connected to internal pull-up resistors.
nWR/DIR
IN nWR is for 80xx CPU, nWR is Write signal input.
Active Low.
DIR is for 68xx CPU, DIR is Bus Direction signal
input. (Low: Write, High: Read.)
nRD/nDS
IN nRD is for 80xx CPU, nRD is Read signal input.
Active Low.
nDS is for 68xx CPU, nDS is Data Strobe signal
input. Active Low.
nRESET
IN Hardware reset signal. Active Low.
nINTR
OUT Interrupt signal output. Active Low.
nCS
IN Chip Select input. Active Low.
nIOCS16
BUSTMG
DREQ
OUT
IN
OUT
This signal is an active Low signal which indicates
accessing 16bit data only by CPU. This signal
becomes active when CPU accesses to data register
only if W16 bit is 1. This signal is same as on ISA
Bus signal, but it’s not OPEN-DRAIN. An external
OPEN-DRAIN Buffer is needed when this signal
connects to the ISA Bus.
Read and Write Bus Access Timing mode selecting
signal. Status of this signal effects CPU and DMA
Timing.
L: High speed timing mode (only for non-multiplexed
bus)
H: Normal timing mode
This signal is connected to internal pull-up registers.
DMA Request signal. Active polarity is
programmable. Default is active high.
6
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